Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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Mahboi

Senior member
Apr 4, 2024
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Apparently there will be only a small number of LP cores. [Purpose: to host background tasks in idle situations/ connected standby maybe — not to prop up Cinebench. ;-) ] Thus, areal density, while not unimportant, may not be a central design goal. For Zen 5LP, that is.
Well duh.
The real question is what will Zen 5 LP do and not do. And what will it do "well enough".

There's a world of difference between a low power core that can scroll through a document or webpage but needs to awaken the big cores on every single new tab or page load, and one that can do web/document editing and possibly also low power video decoding without awakening the rest.
I could easily see a low power islands of 4 Zen 5 LP cores that could still have enough punch to let you watch Youtube/Twitch/Netflix or browse forums or Discord as a total beatdown on the market. 10+ hours of full scrolling/viewing/handling basic tasks without a single worry about battery.

Even if you have to set some limits like say "1080p video decoding but nothing above" or set some "low power mode" in Word or Chrome, you'd have a real monster product.
And with STX Halo you'd also have a strong graphical beast for when you want to play to boot.
 
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APU_Fusion

Senior member
Dec 16, 2013
889
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Wow, it isn’t suspicious at all that rumors zen 5 sucks come out when intel is caught with their hand in the oven … I mean Cooke jar. Even more, just wait Intel will have monster super powerful God chip that makes ai so good you can marry it. Don’t buy slow garbage zen 5. Just wait. Super intel will be out soonish … maybe. 🙄🙄.

This makes me suspect Zen 5 is better than expected and Intel knows it.
 

StefanR5R

Elite Member
Dec 10, 2016
5,633
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The real question is what will Zen 5 LP do and not do. And what will it do "well enough".

There's a world of difference between a low power core that can scroll through a document or webpage but needs to awaken the big cores on every single new tab or page load, and one that can do web/document editing and possibly also low power video decoding without awakening the rest.
Right; how these cores are designed, how they are integrated into the SOC, and how they will be used by OS and userspace — these are all pertinent questions. And the latter question will be crucial, as these cores are going to appear in products which won't be tightly vertically integrated. To put it mildly.

With all the software bloat and data bloat which has been going on for decades now, I have my doubts about the utility of these cores in interactive use. I could be very wrong of course.
 

Joe NYC

Platinum Member
Jun 26, 2021
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Well duh.
The real question is what will Zen 5 LP do and not do. And what will it do "well enough".

There's a world of difference between a low power core that can scroll through a document or webpage but needs to awaken the big cores on every single new tab or page load, and one that can do web/document editing and possibly also low power video decoding without awakening the rest.
I could easily see a low power islands of 4 Zen 5 LP cores that could still have enough punch to let you watch Youtube/Twitch/Netflix or browse forums or Discord as a total beatdown on the market. 10+ hours of full scrolling/viewing/handling basic tasks without a single worry about battery.

Even if you have to set some limits like say "1080p video decoding but nothing above" or set some "low power mode" in Word or Chrome, you'd have a real monster product.
And with STX Halo you'd also have a strong graphical beast for when you want to play to boot.

With decoding resources of the GPU, and the LP cores (both on the Strix Halo SoC), Strix Halo should be able to play video at any resolution without waking up the CPU dies. While running at relatively low clock speeds. For a very decent battery life.

Which probably is the design goal.
 

Mopetar

Diamond Member
Jan 31, 2011
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I wouldn't read too much into anything related to what the market wants based on purchases of Apple hardware. The big APU is just half of the equation and a lot of that big APU is the dedicated hardware acceleration for the sort of things Mac users tend to do with their Macs. The average PC consumer will not do those things making the silicon wasted. Most Mac users won't even light up that silicon on more than a few occasions, but when they do it will at least be fast.
 
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adroc_thurston

Platinum Member
Jul 2, 2023
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I wouldn't read too much into anything related to what the market wants based on purchases of Apple hardware
you should.
It's why LNL-M exists!
and a lot of that big APU is the dedicated hardware acceleration for the sort of things Mac users tend to do with their Macs
no it's just a big APU.
Pro is big and Max is bigger. and Ultra is two taped together.
The average PC consumer will not do those things making the silicon wasted
They don't need media blocks? wowza
Or perhaps even desktops in a post ATX future.
nope.
I think AMD hopes that even luggables will eventually be best served by an APU.
too niche to exist.
 

Joe NYC

Platinum Member
Jun 26, 2021
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I wouldn't read too much into anything related to what the market wants based on purchases of Apple hardware. The big APU is just half of the equation and a lot of that big APU is the dedicated hardware acceleration for the sort of things Mac users tend to do with their Macs. The average PC consumer will not do those things making the silicon wasted. Most Mac users won't even light up that silicon on more than a few occasions, but when they do it will at least be fast.

I think you are trying to prove 2 things at the same time:
- Users don't need a powerful dGPU
- Users don't need a powerful iGPU
Good luck with that.

Strix Halo (and Mac) pose a different question: "Do you really need a costly and power inefficient dGPU if iGPU can do the same job for less money and less power consumption".

Which is a simpler question to answer.
 
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Joe NYC

Platinum Member
Jun 26, 2021
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Naaa, InFO is dog cheap.
Thing is, luggables are a tiny-tiny part of the laptop TAM and taping out a 512b LPDDR SOC tile for them isn't really a good idea.
These can just use dGFX.

Would it kill power efficiency (on mobile) if the memory controllers (with MALL) were on a separate N6 die, connected using InFO?

I guess that by Zen 7 (in ~4 years?), N6 base die will displace InFO for client PC applications, but I wonder what is likely to happen in Zen6 on client side with die partitioning and modularity.
 

adroc_thurston

Platinum Member
Jul 2, 2023
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Would it kill power efficiency (on mobile) if the memory controllers (with MALL) were on a separate N6 die, connected using InFO?
Yeah lmao.
I guess that by Zen 7 (in ~4 years?), N6 base die will displace InFO for client PC applications
Nope.
but I wonder what is likely to happen in Zen6 on client side with die partitioning and modularity.
Have you seen Navi31? I sure didn't!
 

branch_suggestion

Senior member
Aug 4, 2023
244
525
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Naaa, InFO is dog cheap.
Thing is, luggables are a tiny-tiny part of the laptop TAM and taping out a 512b LPDDR SOC tile for them isn't really a good idea.
These can just use dGFX.
Yeah, the tapeout costs and getting different platforms validated combined with the small TAM makes it unviable.
What we have isn't ideal, but it's good enough. Apple can do the funny bit by themselves.
 

Joe NYC

Platinum Member
Jun 26, 2021
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Yeah lmao.

I kind of suspected that...


Intel is doing 3D Hybrid Bond on active base die in Clearwater Forrest in 2025. Granted, it is a server.

What are the odds Intel will do the on client before 2028? Intel is already spending part of the cost on a non-active base die. The cost increment to go to active die with 3D hybrid bond in 4 years? Remains to be seen if it is prohibitive.

Have you seen Navi31? I sure didn't!

I could see different partitioning:

Strix Scenario
- 128 bit (memory width) N6 base die with memory controllers, MALL, IO, analog
- ~20 CU GPU stacked on top ~80 mm2
- 1 or 2 CCDs connected using InFO
- optional NPU die on the other side using InFO

Strix Halo Scenario
- 256 bit or 2x 128 bit N6 base die like above
- ~40 CU GPU stacked on top ~160 mm2
- 2 CCD connected using InFO
- optional NPU die on the other side using InFO

- Desktop, no GPU
- One or 2 of the same N6 base dies
- No GPU stacked
- 2 CCD connected using InFO
- optional NPU die on the other side using InFO

LP cores? not sure where
Base die would have all the IO to allow PCH-less systems.
 

del42sa

Member
May 28, 2013
49
46
91
Here we go with the pointless pictures again.
Wow, it isn’t suspicious at all that rumors zen 5 sucks come out when intel is caught with their hand in the oven … I mean Cooke jar. Even more, just wait Intel will have monster super powerful God chip that makes ai so good you can marry it. Don’t buy slow garbage zen 5. Just wait. Super intel will be out soonish … maybe. 🙄🙄.

This makes me suspect Zen 5 is better than expected and Intel knows it.
[Took a hammer to your crystal ball picture and smashed it]

-Moderator Aigomorla


look into the crystal ball .... best to base your judgment on feelings
 
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