Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Mopetar]

Clockspeed, yields, node? 8c could be on an older node than 16c and 32c so would be quite a bit cheaper. V-cache compatibility.

Those are just off of the top of my head.

The biggest is cost. 8C is a smaller chiplet and there are plenty of consumers who don't even need that many cores.

I think 3D V-Cache is everywhere.

Doubtful unless they've fixed a lot of the performance quirks and are moving the L3 off the base die. V-cache does nothing for most consumer workloads outside of gaming or isn't worth the loss in clock speed it currently brings. Some professional users certainly benefit, but it's not worth the added cost to make everyone pay.

 

[Joe NYC]

Why use 2x8c instead of 1x16c, for the 16c client CPU variants of Zen6?

Assuming there will be 16c CCD of Zen6 available anyway, why not use them on client too? Also opens up for 2x16c on client CPUs, and 1x16c + 1x8c.

Because of 95% of units sold on client will have a single 8 core CCD.

The server CCDs may be optimized for different settings, and also, may not be at all compatible from client style packaging.

So it will still be the most efficient to serve the 95% with single CCD and the remaining 5% with dual 8c CCDs.

 

[Ajay]

Zen5 is already old news. Leaks about Zen6 starting to appear now:

AMD Zen 6 To Feature Three CCD Configurations: 8, 16, & Up To 32 Cores, Zen 5C Packs 16 Cores In Single CCX

AMD's next-gen Zen 5 and Zen 6 core configurations have allegedly been revealed with the latter featuring up to 32 cores per CCD.

wccftech.com

View attachment 99257
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LOL! Zen5 isn't even released yet.

Here's another idea. Start an New Zen6 thread. I'd start it, but I don't know a damn thing.

 

[soresu]

LOL! Zen5 isn't even released yet.

Not even announced yet at that.

We should at least leave Zen 6 thread starting for that.

 

[zacharychieply]

Going to 16 cores on a single ccx would reduce core to core latency, but they will probably need upgrade their ring interconnect to either a 4x4 tile interconnect or something better.

 

[StefanR5R]

Going to 16 cores on a single ccx would reduce core to core latency,

and energy consumption of intra-CCX traffic is lower than that of inter-CCX traffic too. But the workloads in which this matters are rarely seen on client computing devices.

but they will probably need upgrade their ring interconnect to either a 4x4 tile interconnect or something better.

which, in turn, is bound to increase the cache's power consumption, or cache performance will regress (for some access patterns).

 

[CouncilorIrissa]

The thread has cooled down a little.
So what are everyone's final guesses on the perf increase now that Computex is around the corner? I think pretty much everything that could leak already did at this point, and we're not getting any more info until the announcement.

My guess is +21% IPC, +200MHz for top desktop chip, take it or leave it. Zen 3 reloaded basically.

edit: SIR 2017.

 

[Goop_reformed]

The thread has cooled down a little.
So what are everyone's final guesses on the perf increase now that Computex is around the corner? I think pretty much everything that could leak already did at this point, and we're not getting any more info until the announcement.

My guess is +21% IPC, +200MHz for top desktop chip, take it or leave it. Zen 3 reloaded basically.

25%+ st uplift. Higher in synthetic, lower in real world usage. 20% for multi.

 

[StefanR5R]

Re #11,158 and #11,159: Doesn't mean anything if the workload isn't specified.



(And IPC is not the correct acronym for iso-clock performance anyway.)

 

[CouncilorIrissa]

Re #11,158 and #11,159: Doesn't mean anything if the workload isn't specified.



(And IPC is not the correct acronym for iso-clock performance anyway.)

For AMD's marketing "IPC" term is simply short for "iso/clock perf gains at SPEC Int Rate 2017".

 

[Abwx]

The thread has cooled down a little.
So what are everyone's final guesses on the perf increase now that Computex is around the corner? I think pretty much everything that could leak already did at this point, and we're not getting any more info until the announcement.

My guess is +21% IPC, +200MHz for top desktop chip, take it or leave it. Zen 3 reloaded basically.

edit: SIR 2017.

Not easy to draw conclusive estimations out of half baked GB numbers with an ES
or from the Blender bench in unknown conditions.

I will stand with my 22.47% minimal average IPC extracted out of nebulous statistics based on said early numbers and from the alleged uarch evolution.

 

[Philste]

No matter if IPC is the right word or not:

ZEN5: 22-23% IPC, 5.8 GHz for top CPU in Desktop stack

Lion Cove: 17-18% IPC, 5.5GHz max

So my guess is ZEN5 has 10% better singlethread than top ARL and arrived a quarter earlier (or more). ARL will be competitive in multi tho and maybe even more efficient in multi.

Gaming wise, I think both new products will fail to beat their predecessors. ZEN5 because X3D is just too strong, ARL because of horrible Cache characteristics.

 

[APU_Fusion]

I predict 40.0001% ipc uplift in <2 benchmark with ipc uplift of between -10% and 39.9999999% in the rest 🧐

 

[Saylick]

Screw it. Go big or go home.

30% IPC gain with a ~200 MHz increase to peak ST clocks (~5.9 GHz). Gimme dat N4X node.

Multithreaded gains in the low 20% range.

 

[Mopetar]

I'll go with 27% average for the single thread integer workloads. It's not like we're playing by The Price Is Right rules or anything.

 

[Ajay]

+25% average performance uptick based on whatever applications AMD uses on their performance gain slide. Less, boo, more, Yay!

 

[adroc_thurston]

So what are everyone's final guesses on the perf increase now that Computex is around the corner?

fast

Zen 3 reloaded basically.

this is far bigger and meaner than Zen3.

Screw it. Go big or go home.

30% IPC gain with a ~200 MHz increase to peak ST clocks (~5.9 GHz). Gimme dat N4X node.

Multithreaded gains in the low 20% range.

see? this one is close.

 

[CakeMonster]

What about some more relatable predictions? Game performance vs Z4 X3D? Sustained encoding speed with Handbrake? Browser benchmarks?

 

[CouncilorIrissa]

One of these is not like the others.

Browsing performance should be the big winner apparently.

 

[Saylick]

Looks like Zen 5 will be discussed at this year's Hot Chips by Brad Cohen and, of course, Mike Clark.
https://hotchips.org/advance-program/

It's time, Mark. Wakey wakey.

 

[Joe NYC]

and energy consumption of intra-CCX traffic is lower than that of inter-CCX traffic too. But the workloads in which this matters are rarely seen on client computing devices.

Yeah, I am really curious about the use case where this matter, and I can't think of a good one.

The real issue with 2 CCDs (in client) is thread jumping from 1st CCD to 2nd CCD, while all it's cached data is on 1st CCD.

It seems to me that this case can be mittigated by some sort of algorithm that would have awareness of content of both CCD caches, and being able to copy content of L3s between CCDs.

Also, the new packaging for Strix Halo could allow direct (and fast) CCD to CCD communication.

 

[adroc_thurston]

Browsing performance should be the big winner apparently.

Vidya too.
What effectively is a dingus quad-core won a ton of gaming laptops.

Looks like Zen 5 will be discussed at this year's Hot Chips by Brad Cohen and, of course, Mike Clark.
https://hotchips.org/advance-program/

HC in general is insanely stacked this year.

 

[CouncilorIrissa]

Vidya too.
What effectively is a dingus quad-core won a ton of gaming laptops.

HC in general is insanely stacked this year.

Vidya benefits a lot from 3D-cache as well, so not sure if front-end improvements will be big enough to offset that and add some performance on top.

this is far bigger and meaner than Zen3.

Well, wider does not always translate to large perf improvements (*cough* A17 Pro P-cores vs Everest), and leaked memebench numbers, while good, weren't THAT good (obviously those were from ES chips that have all sorts of immature firmware and locks).

 

[adroc_thurston]

so not sure if front-end improvements will be big enough to offset that and add some performance on top.

of course. child's play.

Well, wider does not always translate to large perf improvements

This is AMD we're talking about.

and leaked memebench numbers, while good, weren't THAT good (obviously those were from ES chips that have all sorts of immature firmware and locks).

cinememe isn't a relevant workload. basically doesn't exist as a target for uarch people.

 

[CouncilorIrissa]

cinememe isn't a relevant workload. basically doesn't exist as a target for uarch people.

I was talking about Geekbench, as easily gameable as it is. Not SPEC, but better than Cinebench.