That would have been my first assumption ye.on fp's if the flash portion died the drive was useless when they first came out. the early drives including apple's twist with the fusions were terrible. I don't remember anyone liking those drives.
i never considered the tbw of the flash portion in those days but the sudden failure. ssds are more reliable today than they were then. for a time there popped up services that would fix the ssd portion but it'd cost mint, not an issue if the data was important to you.That would have been my first assumption ye.
Given the NAND $ was much smaller than a regular SSD and in constant write use the failure speed from write wear would be anything but ideal.
Some folks (RetiredEngineer et al) already mentioned Zen 3 'ring bus' is not exactly a ring.My guess is it's some sort of analogue of intel's mesh interconnect. Made to scale past 8 cores in the future. Quick thought:
In our testing, our results show that while AMD’s core complex is not an all-to-all connection, it also doesn’t match what we would expect from ring latencies. Simply put, it’s got to be more than a ring. AMD has been very coy on the exact details of their CCX interconnect – by providing a slide saying it’s a ring reinforces the fact that it’s not an all-to-all interconnect, but we’re pretty sure it’s some form of a bisected ring, a detail that AMD has decided to leave out of the presentation.
To see what kind of nonsense they come up with and to obfuscate what it will be in reality?I am just wondering why would somebody pass on such technical information to YouTubers who are most likely not able to comprehend the significance of it all.
too much effort, give it to a dumb dumb like mlid a malignant disease on tech and he'd mess it up six ways from sunday.To see what kind of nonsense they come up with and to obfuscate what it will be in reality?
A real life example of giving a monkey a typewriter, perhaps? Or maybe they're straight up paid for it. Or there's some middleman just passing on whatever he/she happens to know.But regardless of what it may be, I am just wondering why would somebody pass on such technical information to YouTubers who are most likely not able to comprehend the significance of it all.
Some of it may be that, but likely most of it is the higher ups plugging the leaks by disseminating false information of varying degrees and seeing what ends up on Youtube to know who to yeet with extreme prejudice.To see what kind of nonsense they come up with and to obfuscate what it will be in reality?
Peta would have you flailed alive if they caught wind of you comparing monkeys to people like mlid or that other one.A real life example of giving a monkey a typewriter, perhaps? Or maybe they're straight up paid for it. Or there's some middleman just passing on whatever he/she happens to know.
Nothing about this roadmap strikes me as obviously fake, at least. There are a couple of interesting details, though. Leading with Zen 5c instead of Zen 5 is notable, and naturally draws parallels to Intel's similar strategy with Sierra Forest vs Granite Rapids. "Turin AI" is new, so that will be interesting. Swapping a CPU chiplet with an AIE-ML one?So, MLID has insider slide of Zen5 release date? Should we believe him this time?
AMD Ryzen 8000 CPUs Specs and Launch Date: Up to 16 Zen 5 Cores, 64MB L3 Cache, 1H 2024 Launch [Rumor] | Hardware Times
AMD’s next-gen Zen 5 processors are expected to launch shortly after the recently released Zen 4 products. With a major rework of the front end, it is said to offer a drastic performance uplift over existing lineups. While the consumer-based Zen 4 offerings are already out and about, many Data...www.hardwaretimes.com
View attachment 80596
did i miss something because from what i can make out base z5 aka granite ridge is showing up as beginning midway of q1 into q4 which i assume is a window of release or were you referring to something else?Nothing about this roadmap strikes me as obviously fake, at least. There are a couple of interesting details, though. Leading with Zen 5c instead of Zen 5 is notable, and naturally draws parallels to Intel's similar strategy with Sierra Forest vs Granite Rapids. "Turin AI" is new, so that will be interesting. Swapping a CPU chiplet with an AIE-ML one?
Above all that however, it looks like the base Zen 5 cadence is staged a full 2 years after Zen 4. That's a bit later than we might have liked. Seems like the longer Zen 4 timeline might not have been a one-off.
And as a last note, something is weird with that 'Turin-X' box. Wonder what was blacked out.
I think the right hand side of the box is what matters, given that it's marked as "prod". The rest is likely either meaningless, or some sort of post-silicon timeline.did i miss something because from what i can make out base z5 aka granite ridge is showing up as beginning midway of q1 into q4 which i assume is a window of release or were you referring to something else?
First of all the question remains how many stops that ring has. Is the IFoP a separate stop or is it directly connected to the L3 somehow?Some folks (RetiredEngineer et al) already mentioned Zen 3 'ring bus' is not exactly a ring.
Ian Cuttress also noticed from his tests the interconnect is not exactly a ring.
The consensus is that it is a bisected ring like below. Cores are placed on all the periphery of the ring unlike as depicted.
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Does an AMD Chiplet Have a Core Count Limit?
www.anandtech.com
So the ladder interconnect could be a double/triple bisected ring which would probably be an extension of the current interconnect.
But regardless of what it may be, I am just wondering why would somebody pass on such technical information to YouTubers who are most likely not able to comprehend the significance of it all.
that makes no sense. the chart shows genoa coming out in q3's timeline this was not the case it was a late q4 product launch. Genoa x is also far too early on that chart and we're well into q2 now. Bergamo is a mes too. i figured a way to enlarge the photo upload there is a 2nd note stating these are production targets not timelines but was is more confusing is raphael on am5 is listed towards the end of 2023 and not 2022. either mlid is making crap up which is no surprise to anyone with a single brain cell or he's been had, or he's been had and is too dumb to notice any of the errors.I think the right hand side of the box is what matters, given that it's marked as "prod". The rest is likely either meaningless, or some sort of post-silicon timeline.
Always believe the good news and shout them from the rooftops.So, MLID has insider slide of Zen5 release date? Should we believe him this time?
As I just realized, I of course messed up the calculation. The average hops for the ring should be correct, but the number for the bisectional ring is too low. I always forget that for a non uniform topology (more or less everything except ring and star) it is not sufficient to use just one node as the source for the counting and consider all others being equal.If the (bidirectional) ring only has 8 stops, then average hops already are pretty low with around 2.3 hops (if I did not mess up calculation). A bisection would further reduce this to 1.6.
No, that makes perfect sense. Officially launching about a quarter after they start volume production is more or less the standard timeline. Plus, they start shipping to a few customers ahead of the launch event.that makes no sense. the chart shows genoa coming out in q3's timeline this was not the case it was a late q4 product launch.
I think that's meant to be the Ryzen Embedded parts, given that this is a server roadmap. The Vermeer ones just launched a few weeks ago, so the timing makes sense.but was is more confusing is raphael on am5 is listed towards the end of 2023 and not 2022
A split ring (bisected), just means two rings - with one 'stop' (switch/router) from each ring to the other. 2 actually, for c-w and cc-w; but still just one stop for computing latency. You also need a 'node' for the IF connection to the ring (again, two of them). There is a math formula for it, but I don’t recall it at the moment. So, just start at node n=1 to n=10 and sum the latency for each node to the other, then divide by 10. I’m sure the route uses SPF (shortest path first). AMD could probably just make the IF node another route point - but I don’t know if they do. Intel had separate points for memory, I/O and ring to ring connections.As I just realized, I of course messed up the calculation. The average hops for the ring should be correct, but the number for the bisectional ring is too low. I always forget that for a non uniform topology (more or less everything except ring and star) it is not sufficient to use just one node as the source for the counting and consider all others being equal.
On that occasion I miserably failed in finding a calculator for such things on the World Wide Web. Does anyone know of such a calculator where you can enter the number of nodes, topology, directionality, etc. and get the average hops?
or push him off one.Always believe the good news and shout them from the rooftops.
Repent later.
Whoooaaa there camel 😅or push him off one.
who keeps leaking stuff to that guy? is there a larger version of that picture for those of us with terrible eyesight?
Paul?If I were JHH, Lisa, or Paul I'd call him up and personally feed him complete BS just for laughs. It's like the old "No one will ever believe you" Bill Murray meme.