3D V-Cache solves this, and the economics are very simple. The cost of the hybrid bonding/packaging just has to be less than the cost difference between the N and N-1 (or even N-2) processes times their respective area scalers. I see that as a very realistic possibility within a few years.
I have not gotten time to read the manuals properly, I was/am in multiple webex meetings. I will be editing the post.Your #DF quote has nothing to do with the rest of your post. Double fault is a feature of 80286 and later and is invoked when a fault happens while processing another fault. The "interrupt/exception transfer" it speaks of is about transferring execution from one portion of code to another (i.e. from faulted code to the fault handler).
As such, I disagree with your conclusion. While heterogenous cores might be coming, there is no indication of seamless transfer (at least not with the source you provided).
The updated Architecture Programmer's Manual is available from the usual place in case you can check for other changes as well:at least not with the source you provided
Not joking. Even if AMD list patents about big_little RIGHT NOW, at the earlist it would be implemented several years later. Zen5 and more likely Zen6 which are based on AM5 would still be all BIG core design, I don't think AMD would implement big_little on AM5 since there's too little space inside the lid, Intel design its LGA1700 package as rectangle so it could add E cores with no brainer.
If AMD do, they should have warn us already. I don't see anything related to hybrid design coming with Zen5. Also Zen4C means Cloud edition.16 Zen 4c cores are about the same size as 8 Zen 4 cores. Doing 8 Bigger cores and 16 big cores shouldn't be a problem.
Source? I don't believe we've seen a die shot of Zen 4c yet.16 Zen 4c cores are about the same size as 8 Zen 4 cores. Doing 8 Bigger cores and 16 big cores shouldn't be a problem.
If AMD do, they should have warn us already. I don't see anything related to hybrid design coming with Zen5. Also Zen4C means Cloud edition.
Source? I don't believe we've seen a die shot of Zen 4c yet.
Considering that they did not even release manual for Zen 4 on time, they usually add stuffs in the manuals when they need to upstream code. Because maintainers do not accept to merge code in a common code base like x86 unless they have a reference to a public document. So with this Manual reveal, you should expect to see these features in an upcoming CPU and new patches need to be upstreamed. That is the only reason they share manuals, or when there are vulnerabilities and mitigations needed. Intel is far more open when it comes to sharing manuals of upcoming CPUs.Not joking. Even if AMD list patents about big_little RIGHT NOW, at the earlist it would be implemented several years later. Zen5 and more likely Zen6 which are based on AM5 would still be all BIG core design, I don't think AMD would implement big_little on AM5 since there's too little space inside the lid, Intel design its LGA1700 package as rectangle so it could add E cores with no brainer.
That doesn't mean the die size will the same. Really, it doesn't tell us much of anything.Now if the rumors are correct, which seem plausible, Zen 4c will contain half the cache and will have 16 cores per chiplet divided into two CCXs.
Zen 4c/5c would not make sense as the only core for mainstream mobile parts. Need the single thread performance of the high speed implementation.Given that AMD has been capacity limited, and the fact that they are adding a separate high-end desktop-like mobile processor, providing the laptop market with a significantly cheaper chip due to density improvements makes a lot of sense. And why two CCXs per chiplet? Reusable 8-core CCX for a monolithic laptop design...
From my understanding of the TSMC SoIC roadmap, there is no N7/N6 on N3. Just N5 on N3.Exactly. If Zen 5 is on N3, it could very well be difference between N and N-2 process node.
And as I suggested above, for the cost of certain amount of SRAM on N3, AMD might be able to get 3x that amount of SRAM on N6.
The second AMD said Zen5 would be dual process i thought this was a likely possibility. IF Zen5 APU was comming a year later what product would they want to limit to a by then very old processSkyJuice seems to think Strix Point is 2024, which given past behaviour likely means CES, so January 2024. While his/their credibility has been great do far, can't help but notice some of the leaks/claims are odd, maybe even fishy.
Anyway, asuming that were true, would AMD launch mobile Zen5 first? That'd be interesting. We'll probably be getting a big dump of Turin info in H2 next year, from both official and 3rd party channels.
I didn't imply that (but personally I was expecting it to come a bit more ahead of AD).
But this makes the "Christ is returning hype" even worse. If Zen 4 improved so much with so little effort than the Earth will Stood Still to witness Zen 5 launch.
Maybe this is a consequence of Zen 1 real performance.
I remember people expecting much less before launch but it surpassed everyone's expectations a bit. Except Zen+ every generation got better and this got people used to expect the most ludicrous rumors (just think how much people still give time and attention to "that" youtube channel).
The good times are over, now AMD still alone anymore, Intel is back into competition.
That doesn't mean the die size will the same. Really, it doesn't tell us much of anything.
Zen 4c/5c would not make sense as the only core for mainstream mobile parts. Need the single thread performance of the high speed implementation.
Zen 3 was absolutely a new core. Didn't Keller say something about K12 learnings making their way into it?Zen 3: (optimize) IPC focus, slight clock increase driven by optimization.
Compared to what tho? Zen2 was compared to both Zen and Zen+, the 15-16% IPC is vs Zen and 12-13% vs Zen+. Taking gen on gen as the metric (which would be the most rational metric IMO), Zen2/R3000 vs Zen+/R2000 achieved the same IPC/PPC as Zen4/R7000 vs Zen3/R5000. 13%"Slight" IPC jump for Zen 4 is 13%, which is a hair lower than Zen 2 IPC gains
Well the 13% is clearly compared to Zen 3, which has already brought huge 19% gain previously. Similarly, 15% on top of Zen1 (what Zen 2 did) is also a big jump.Compared to what tho? Zen2 was compared to both Zen and Zen+, the 15-16% IPC is vs Zen and 12-13% vs Zen+. Taking gen on gen as the metric (which would be the most rational metric IMO), Zen2/R3000 vs Zen+/R2000 achieved the same IPC/PPC as Zen4/R7000 vs Zen3/R5000. 13%
Contextually and at that time, the Zen2 IPC/PPC improvements weren't considered just "slight" at all. Particularly because they also beat Skylake by 11% or so.
Zen 3 was the last gen where Keller was still involved in early planning. As for K12, I recall a mention that members of the ARM K12 team went on to handle Zen 3 and 4. As we know x86 K12 turned into Zen.Zen 3 was absolutely a new core. Didn't Keller say something about K12 learnings making their way into it?
"Zen 3" is the first major microarchitectural redesign in the AMD Zen family of microprocessors. Given the same 7nm process technology as the prior-generation "Zen 2" core, as well as the same platform infrastructure, the primary "Zen 3" design goals were to provide: 1) a significant instruction-per-cycle (IPC) uplift, 2) a substantial frequency uplift, and 3) continued improvement in power efficiency.
I would bet in four CCX per chiplet, with 4 cores per CCX. Why? Because it would be reusable for lower end monolithic mobile cpus, like Mendocino and Steam Deck's APU that right now are stuck in Zen2 because Zen3 and Zen4 are 8-core CCX. 8 big cores is too much leakage for those power limited designs (see 6800U sometimes losing to Steam Deck at 15W or less) that don't need that much multithreaded performance anyway. The lower clock and power targets are also perfect for those CPUs. Higher power and performance mobile CPUs can use the regular 8-core CCX Zen4 design.And why two CCXs per chiplet? Reusable 8-core CCX for a monolithic laptop design...
big.BIG is confusing. I know what you mean but suppose Zen 5 is heterogenous the big cores that were in Zen 4 will be little in Zen 5 and even bigger cores will come to Zen 5. It's either big.LITTLE or hybrid.Heterogenous cores are coming, and it is officially added in the manuals. big.BIG is real.