For such a radical design, I would expect a lot more than 15% gain to be worth the risks and power usage and not to mention possible security implications.
a) that's nT IPC (basically per-vCPU iso clk perf)I can’t reconcile it in my head that such a massive change only amounts to an IPC increase of 10-15%
7-10% (got 13%) and 8% (got 14%).I really wish we could see the internal estimates for Zen 3 & 4 pre-launch to get an idea of how this went in the past.
Late March or April.What again is your best guess for Zen 5 desktop availability (to buy) ?
Your trolling and personal attacks against @adroc_thurston are not adding any value to this thread.Correct. And there will be Zen5 AM5 desktop SKUs with:
2xZen5 8C = 16C
1xZen5 8C + 1xZen5C 16C = 24C
2xZen5C 16C = 32C
Just called Lisa Su and double checked. Apparently it hasn't rippled down through the hierarchy to adroc_thurston yet.
Your trolling and personal attacks against @adroc_thurston are not adding any value to this thread.
Yeah you shouldn't, I just buy stuff.Why are we treating @adroc_thurston as some sort of insider
I was talking about Nov 2023.A certain someone on these forums is saying H1 2024. November might be when the X3D parts are released, to rain on Intel's Arrow Lake parade.
Think he is talking SPEC int Rate for server parts, which my quick google gives about 13% for zen 2 to 3 , i cant find good zen 3 to 4 numbers.Zen3 was 19%.
Think he is talking SPEC int Rate for server parts, which my quick google gives about 13% for zen 2 to 3 , i cant find good zen 3 to 4 numbers.
assuming the theme keeps from the original MLID image
IPC wise, looking at a histogram of all SPEC workloads, we’re seeing a median of 18.86%, which is very near AMD’s proclaimed 19% figure, and an average of 21.38% - although if we discount libquantum that average does go down to 19.12%. AMD’s marketing numbers are thus pretty much validated as they’ve exactly hit their proclaimed figure with the new Zen3 microarchitecture.
1t.Zen3 was 19%.
AMD had those in their HC'23 Zen4 session but idk if you have the access to it.i cant find good zen 3 to 4 numbers.
That is 1t.Numbers from AT, although it was less than 19% in Cinebench...
1t.
nT scaling iso clock was a lot less, and Milan clocked less iso power on top of that.
AMD had those in their HC'23 Zen4 session but idk if you have the access to it.
That is 1t.
No lol.Whatever, it means that the numbers in the recent slide, wrong or right, are also for 1T.
No lol.
That's not server.That s surely some average like these ones :
That's not server.
Christ.
No, it's just whatever they have for 1st party measurements in server, and they never presented nT IPC for Milan since it sucked so they plugged the client number in.but this is close enough that they could retain the higher number for the purpose of exhibiting the higher possible one on the slide.
No, it's just whatever they have for 1st party measurements in server, and they never presented nT IPC for Milan since it sucked so they plugged the client number in.
Not the issue, the thing just had negative PPW over Zen2 in silly nT loads.For Zen 3 they were stuck with DDR4 wich didnt help for high core count SKUs but was good enoygh for DT CPU
Those were my expectations, turns out to be more.if the uarch slide is accurate then it should be something like 20-22%.
ALU count is a rather silly metric.Historically they improved IPC by 52% with 100% more ALUs, with 50% more the number is unlikely to be as low as the 10-15% that was leaked, Intel got as much by increasing the ALU count by a mere 33%, 3 ALUs to 4, from SB/IBridge to Haswell.
Not the issue, the thing just had negative PPW over Zen2 in silly nT loads.
X4 has 8 of them and isn't that much faster over 4ALU X1.
So @adroc_thurston what is your rough IPC range for Zen 5 if it is more than 22%Not the issue, the thing just had negative PPW over Zen2 in silly nT loads.
Those were my expectations, turns out to be more.
ALU count is a rather silly metric.
X4 has 8 of them and isn't that much faster over 4ALU X1.
Milan.5950x clocked 3.3% higher in MT than the 3950X, just this clock uplift will eat 5% perf/Watt comparatively.
ARM Cortex-X1 and Cortex-X4.What are you talking about here..?..
Very hard without blowing up the power/area budgets.It is easier to extract more performance from FP code
Historically INT was more difficult to improve, but let s look at Zen 4 over Zen 3, first with FP and then with INT.It is easier to extract more performance from FP code than x64 integer code. So 10-15% IPC for integer code seems reasonable, for FP code there is no immediate limit. Most FP code are streaming in nature, so there is high possibility to extract more IPC from FPU. The next big IPC improvement for integer code will come with new CPU design which contains support for 32 Genaral Purpose registers. With increased register count, there is more opertunity to execute parallel instructions.
I provided numbers for the 3950X/5950X, those should be comparable for server parts, overall MT perf/watt was improved by roughly 15% despite slightly higher frequency and a comparable 7nm process.Milan.
7713 vs 7742 is ehhh.
ARM Cortex-X1 and Cortex-X4.
Jesus.
No they aren't, jfc.those should be comparable for server parts
Yes it is, lol.ARM is not a comparable design,