Hmm, now we are dealing with 2 different dies of Strix Point; instead of cutting core counts, AMD decided to cut half amount of L3 cache of Zen 5C, interesting. At least we have clearer picture of what the mobile APU lineup in 2024:-I wonder if he would want to wake up if he realize he will get single digit percentage gains . [15% IPC gain + supposed 5 % clock regression = paltry 9% perf gain.]
Besides that, core uarch update seems really interesting. Biggest update since Zen 1 for sure.
I would have like to see more updates on the SoC architecture but looks like another long wait.
16M SLC on 8C Strix Zen 5c with 8WGP RDNA3+ would have been great for a lot of these Windows handhelds otherwise.
Strix seems to be getting a huge bump on AIE tiles and +33% CUs.
View attachment 86599
Curious whether they will put SLC/MALL all around for Zen 6. I have seen several MALL prefetch patents.
| 2024 | TDP | Node | Die Size | P-core | E-core | Total L3 Cache | RDNA3+ | ALU | AIE | Memory BW |
|---|---|---|---|---|---|---|---|---|---|---|
| Ryzen 5 U-series | ? | N4P | ? | ? x Zen5 | 8xZen5c 8 MB | ? MB | ? | ? | ? | 128-bit 8533 |
| Ryzen 7 U-series | 28-35W+ | N4P | 225 mm2 | 4 x Zen5 16 MB | 8xZen5c 16 MB | 32 MB | 8 WGP | 1024 | 64 | 128-bit 8533 |
| Ryzen 7 HS-series | 45W+ | N4P | 225 mm2 | 4 x Zen5 16 MB | 8xZen5c 16 MB | 32 MB | 8 WGP | 1024 | 64 | 128-bit 8533 |
| Ryzen 9 HS-series | ? | N4Px2 + N3E | ? | 16xZen5 64 MB | NA | 64 MB | 20 WGP | 2560 | ? | 256-bit 8533 |
| Ryzen 9 HX-series | 55W+ | N4Px2 + N6 ? | ? | 16xZen5 64 MB | NA | 64 MB | ? | ? | NA | 128-bit |
Zen 6 will likely still use AM5.I may have missed this, but were there any assumptions on whether Zen 6 will require a new socket?
Just curious of what actual AM5 lifespan is.
Oh I didn’t mean to imply as much. “Announce” was what I was referring to, though you are right we could just get a teaser. Usually parts follow the announcement after a period of weeks or months, so March - May are probably good bets. I have not actually seen any solid leaks for that timeline, however. The only leak I have seen that was reliable indicated late 3rd quarter.I'm afraid there would be no Zen5 at January. Only teaser.
OTOH, few months ago Zen5 DT completion had been already planned to be Oct-Nov, mass production could happen at this timeframe, and there were about 4 months gap between completion to release since Zen2, so you can expect the actual release could happen in 1H2024 or even as early as Mar-Apr.
Mass production could even happening right now when I type this message.
Very rarely will that ever be the case. When it is, the issue is usually either a failure to optimize the first iteration or the introduction of new power management features (or both)Also doesn't disprove that there are instances where a change can both increase IPC and reduce power consumption, which is very obviously true. Practically anything that reduces the need to move up the memory hierarchy may do that, or anything that reduces communication distances/hops, and of course not all work is created equal and it's possible to do more or less work to achieve a result. A more general approach to finding a result can both perform worse and consume more energy than a more specific approach. It's of course possible to do more work with less active transistors and vice versa. And then there's pipelines, branch prediction (which is huge, mispredictions are extremely expensive), OoO etc.
It's not a claim any engineer would make.
Zen 3 is a perf/watt champ, but those charts show exactly what we are referring to. IPC is up, but so is power. That is why the big upgrades often happen after node shrinks. Shrinks drop power/die area, increasing the budget for more transistors, which allow for IPC upgrades.Zen 3 vs. Zen 2
- 19% IPC increase
- same node class, but improved
- slightly higher clocks
- bigger die
- ISO power
- right in our face
The biggest problem in this thread isn't this discussion point though, but rather whether folks around here are going to accept the rude verdicts of a poster as gospel or demand the minimum of proof and decorum.
To be honest I'm sort of baffled of how people here treated mlid like he's an anti-christ. He definitely has good infos and people who are into tech news watch him religiously. Right after a new video is posted, a member linked that here almost instantly. I used to think people hate watch him but my opinions have been swayed.
From a platform perspective are we expecting new 770/750 chipsets?
No.
Why?
Very rarely will that ever be the case. When it is, the issue is usually either a failure to optimize the first iteration or the introduction of new power management features (or both)
Absent those two things, increasing IPC means increasing transistors, which means increasing power consumption.
Zen 3 is a perf/watt champ, but those charts show exactly what we are referring to. IPC is up, but so is power.
I agree. It would almost be idiotic for AMD not to have a new chipset for Zen5. Maybe they tweak it, maybe they don't, but how are motherboard manufactures going to name their new mobos without a new chipset?The motherboard vendors probably want a new model name. If they do, I can't see AMD not supporting their partners with one.
The reason is that Zen4 can currently support much higher memory clocks than it could at launch. Memory clock speed is a selling point printed in large type on MB packaging, and most current models only have 6400+, which was what it was possible to test when the motherboards were released. So MB vendors want to refresh their lineups, and when they do that, they usually want to have a new chipset name.
It's entirely possible that the chipset in question is literally PROM21, just rebranded.
Also seems like mlid has friends on this forum (or his own accounts) promoting his videos.
Zen5 doesn't have any new I/O what's the point of a new chipset?I agree. It would almost be idiotic for AMD not to have a new chipset for Zen5. Maybe they tweak it, maybe they don't, but how are motherboard manufactures going to name their new mobos without a new chipset?
ROG CROSSHAIR X670 E++ MAXIMUM OVDRIVE EDITION???
Zen5 doesn't have any new I/O what's the point of a new chipset?
It shows a mix, mostly because Zen3 runs at a higher frequency but has better voltage scaling. Taken as a whole, running clock-for-clock, volt-for-volt, Zen3 probably runs a bit hotter, but that's taking into account the aggregate changes.
| ST | SMT multipier | MT | |
| Zen3 | 1.000 | 1.250 | 1.250 |
| Zen4 | 1.110 | 1.285 | 1.426 |
| Zen5 | 1.476 | 1.150 | 1.697 |
esentially the same math as I did here yesterday lolI was reading this AT article on SMT scaling for Zen 3, and this quote piqued my interest:
"But, if a core design benefits from SMT, then perhaps the core hasn’t been designed optimally for a single thread of performance in the first place. If enabling SMT gives a user exact double performance and perfect scaling across the board, as if there were two cores, then perhaps there is a direct issue with how the core is designed, from execution units to buffers to cache hierarchy. It has been known for users to complain that they only get a 5-10% gain in performance with SMT enabled, stating it doesn't work properly - this could just be because the core is designed better for ST. Similarly, stating that a +70% performance gain means that SMT is working well could be more of a signal to an unbalanced core design that wastes power.
This is the dichotomy of Simultaneous Multi-Threading. If it works well, then a user gets extra performance. But if it works too well, perhaps this is indicative of a core not suited to a particular workload. The answer to the question ‘Is SMT a good thing?’ is more complicated than it appears at first glance."
Now looking forward to Zen 5, if the slide from mlid is for nT server workload and we assume AMD is sandbagging a bit (let's assume it's +20% higher MT performance at ISO clocks, or in other words 20% higher MT IPC), then below could be Zen 5's performance versus Zen 3 and Zen 4:
ST SMT multipier MT Zen3 1.000 1.250 1.250 Zen4 1.110 1.285 1.426 Zen5 1.476 1.150 1.697
So 33% higher ST IPC vs Zen 4 , core that is designed for ST supremacy, but as a consequence of that, scales much less with SMT (almost a half of the % that Zen 4 gets from SMT : ~28.5% vs 15%). I guess that the total MT throughput performance (at ISO core count and clocks) will greatly depend on what all core turbo speeds the Turin parts can achieve at the given TDP. If TDP is +25%, I think it's possible that we might see similar all core Turbo clocks as we had in Genoa case. That would translate to :
Turin classic vs Genoa classic: 128/96 x 1.2 = 1.6 or 60% more MT performance ; 0.95 x 1.33 = 1.26 or 26% higher ST performance (assuming 5% ST clock deficit vs Genoa)
Turin dense vs Bergamo (both with SMT) : 192 / 128 x 1.2 = 1.8 or 80% more MT performance ; 1 x 1.33 = 1.33 or 33% higher ST performance (assuming no ST clock deficit vs Bergamo)
If they actually had a new chipset, it could significantly better. The links from the CPU are all PCIE 5.0, a better chipset could provide twice the throughput.
But what Ajay and I are proposing is that the reason is just literally marketing. New x770 motherboards will seem fancier than last-gen x670 ones. Even if it's the same chip. There are reasons why vendors do rebrands.
As @Tuna-Fish pointed out, this must be done, at a minimum, for marketing purposes. At least in the DIY space anyway. As he also pointed out, there are still technical reasons to do so, even if the I/O configuration on the CPU itself hasn't changed. AMD may opt to not spend another dime on the chipset - their choice obviously, but I'd be shocked if they didn't rename it.Zen5 doesn't have any new I/O what's the point of a new chipset?
There are always tradeoffs, and time to market for Zen 5 is one of those tradeoffs.As @Tuna-Fish pointed out, this must be done, at a minimum, for marketing purposes. At least in the DIY space anyway. As he also pointed out, there are still technical reasons to do so, even if the I/O configuration on the CPU itself hasn't changed. AMD may opt to not spend another dime on the chipset - their choice obviously, but I'd be shocked if they didn't rename it.
TSMC’s N7P uses the same design rules as the company’s N7, but features front-end-of-line (FEOL) and middle-end-of-line (MOL) optimizations that enable to either boost performance by 7% at the same power, or lower power consumption by 10% at the same clocks.
Its a only a few AM5 motherboards that can run 8000MT/s stable in 2:1 mode, pretty much only two 1DPC from Asus and Gigabyte atm...Zen5 doesn't have any new I/O what's the point of a new chipset?
it doesSame 7nm technology doesnt imply that it s the same 7nm process,
Then AMD would say "different TSMC 7nm finfet technology as Zen 2"N7 and N7P are both based on the same 7nm process.
Better archIf we look at the 5950X vs 3950X the former has 20% better perf/watt at isoclocks, this is a hint that these are not the same iteration of 7nm.
This all makes sense but makes me wonder.. why keep SMT then? If there’s a meager 15% uplift from SMT, is it really worth the trade offs at that point? Getting rid of it reduces a lot of security and validation hurdles.I was reading this AT article on SMT scaling for Zen 3, and this quote piqued my interest:
"But, if a core design benefits from SMT, then perhaps the core hasn’t been designed optimally for a single thread of performance in the first place. If enabling SMT gives a user exact double performance and perfect scaling across the board, as if there were two cores, then perhaps there is a direct issue with how the core is designed, from execution units to buffers to cache hierarchy. It has been known for users to complain that they only get a 5-10% gain in performance with SMT enabled, stating it doesn't work properly - this could just be because the core is designed better for ST. Similarly, stating that a +70% performance gain means that SMT is working well could be more of a signal to an unbalanced core design that wastes power.
This is the dichotomy of Simultaneous Multi-Threading. If it works well, then a user gets extra performance. But if it works too well, perhaps this is indicative of a core not suited to a particular workload. The answer to the question ‘Is SMT a good thing?’ is more complicated than it appears at first glance."
Now looking forward to Zen 5, if the slide from mlid is for nT server workload and we assume AMD is sandbagging a bit (let's assume it's +20% higher MT performance at ISO clocks, or in other words 20% higher MT IPC), then below could be Zen 5's performance versus Zen 3 and Zen 4:
ST SMT multipier MT Zen3 1.000 1.250 1.250 Zen4 1.110 1.285 1.426 Zen5 1.476 1.150 1.697
So 33% higher ST IPC vs Zen 4 , core that is designed for ST supremacy, but as a consequence of that, scales much less with SMT (almost a half of the % that Zen 4 gets from SMT : ~28.5% vs 15%). I guess that the total MT throughput performance (at ISO core count and clocks) will greatly depend on what all core turbo speeds the Turin parts can achieve at the given TDP. If TDP is +25%, I think it's possible that we might see similar all core Turbo clocks as we had in Genoa case. That would translate to :
Turin classic vs Genoa classic: 128/96 x 1.2 = 1.6 or 60% more MT performance ; 0.95 x 1.33 = 1.26 or 26% higher ST performance (assuming 5% ST clock deficit vs Genoa)
Turin dense vs Bergamo (both with SMT) : 192 / 128 x 1.2 = 1.8 or 80% more MT performance ; 1 x 1.33 = 1.33 or 33% higher ST performance (assuming no ST clock deficit vs Bergamo)
looks at LNCThis all makes sense but makes me wonder.. why keep SMT then? If there’s a meager 15% uplift from SMT, is it really worth the trade offs at that point? Getting rid of it reduces a lot of security and validation hurdles.
Starting to think they had the right idea. For client it makes a lot of sense to get rid of it.looks at LNC
Expect that both, Intel and AMD will ditch the SMT from their mainstream CPUs.This all makes sense but makes me wonder.. why keep SMT then? If there’s a meager 15% uplift from SMT, is it really worth the trade offs at that point? Getting rid of it reduces a lot of security and validation hurdles.