Yeah it's not hard, but GB6 is worthless now since you can pump matrix matth subtest with shared accelerators.
Geekbench 5 ain't any better as it includes AVX512 to pump up scores. So any non-Intel (ex 11th gen) and ARM CPUs will score lower.They seem to be continuously fudging Geekbanch 6, so not my favorite, but here it is anyway:
Zen3 did that with barely any area investment.I think it will be closer to +20%.
Also crypto.Geekbench 5 ain't any better as it includes AVX512 to pump up scores. So any non-Intel (ex 11th gen) and ARM CPUs will score lower.
Zen 3 is a new and better design than Zen 2, adding approximately 15% more transistors to the core logic (excluding L2).Zen3 did that with barely any area investment.
It didn't.
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I've literally posted AMD's ISSCC breakdown on Zen3.
What do you think the 3D-V cache does if it doesn't allow the average to get closer to the theoretical maximum of the core microarchitecture?I've literally posted AMD's ISSCC breakdown on Zen3.
I've literally posted the detailed breakdown of microarchitectural updates contributing to Zen3 IPC uplift.What do you think the 3D-V cache does if it doesn't allow the average to get closer to the theoretical maximum of the core microarchitecture?
You can just subtract 9-10% from the Apple score for the non-AMX value.Any predictions if Zen 5 can match Apple M4 Geekbench 6 score that has been posted, in single thread? They seem to be continuously fudging Geekbanch 6, so not my favorite, but here it is anyway:
M4: ~3800
7950: 3068
I know this graphic (since it was published online) with a percentage breakdown of how much is allocated to a given part of the core.I've literally posted the detailed breakdown of microarchitectural updates contributing to Zen3 IPC uplift.
Deck's 2yo and public.
No, they're literally the things responsible for the IPC uplift.how much is allocated to a given part of the core.
So why does AMD provide an IPC increase for games in Zen 3, when it is known that this applies to a larger number of cores, e.g. 8, and where it is known that the increase will result from a common and large L3 for all 8 cores without division into CCX? Can you explain this to me?No, they're literally the things responsible for the IPC uplift.
Because those are branchy membound workloads, Zen3 new BP with bigger BTBs did wonders there.So why does AMD provide an IPC increase for games in Zen 3,
There are no miracles, otherwise you could say it's a miracle that it works. If you hypothetically cut off all L3 memory, wouldn't the performance drop be an IPC drop? Will BTB make up for it too?Because those are branchy membound workloads, Zen3 new BP with bigger BTBs did wonders there.
Power usage is going up quite a bit for DT SKUs. It’s unclear if it’s an accident or not but there’s numerous instances where DT 8C SKU has a listed TDP of 170W.The following is ONLY from the perspective of a Distributed computing perspective. This means 2 things, computing power and efficiency. We use all cores and most of the time SMP.
Zen 1 : way better than bulldozer in all respects, and if I remember correctly cheaper and more efficient than the Intel counter parts.
Zen 2 : small improvements in performance, about the same efficiency as Zen 1.
Zen 3 : MUCH better performance AND efficiency compared to Zen 2 The larger L3 cache made a big difference in some apps.
Zen 4 : MUCH better performance than Zen 3, but about the same efficiency. But in apps that use avx-512, nothing could touch the performance. For primegrid, we had to disable SMT and pin cores to a CCX for maximum performance, but when we do, nothing that Intel has comes close.
Zen 5 : Most of us anticipate that it will be the same in efficiency, but far better in performance.
Again, speaking for the DC community and that means 100% load 24/7/365. And yes, the electric bill means more to use than any other group of users.
efficiency is the key. If an 8 core Zen 5 performs better than a 16 core Zen 4, then it would be worth it to us.Power usage is going up quite a bit for DT SKUs. It’s unclear if it’s an accident or not but there’s numerous instances where DT 8C SKU has a listed TDP of 170W.
I don't care about hypotheticals, you have detailed microarch breakdown from AMD.If you hypothetically cut off all L3 memory, wouldn't the performance drop be an IPC drop
The division on the slide is of a marketing nature and is not very insightful. It doesn't take cache into account at all because specific parts of the core are responsible for retrieving data.I don't care about hypotheticals, you have detailed microarch breakdown from AMD.
C&C you will also read about solutions advertised by AMD that are presented as unique but in fact are not.It's for ISSCC. From the people who designed it. I'll take that over 'a gamer explains'.
There's a reason AMD markets the X3Ds as 'the ultimate in latency reduction' not 'the ultimate in IPC'.
Yes but your going to see that covered by the prefetch and load parts of the breakdown diagram. But that will only be a component of those sections.C&C you will also read about solutions advertised by AMD that are presented as unique but in fact are not.
Latency reduction is part of measurable IPC because it causes the core logic to wait less for data and can therefore execute more instructions at the same time.
You just forgot that a V-cache is used by 8 cores, it s not single core IPC wich is improved but only MT throughput with some select apps, if you do a ST test you ll see that the score is the same with and without V-cache.C&C you will also read about solutions advertised by AMD that are presented as unique but in fact are not.
Latency reduction is part of measurable IPC because it causes the core logic to wait less for data and can therefore execute more instructions at the same time.
It's from ISSCC.The division on the slide is of a marketing nature and is not very insightful
Sort of.The truth is that the cache and RAM of the controller are part of the measurable IPC