For serious AI work you'll want a top end workstation if you're doing the work locally. If you aren't a $200 Chromebook that can SSH into a workstation is about as good as anything else.
see?Memory capacity is king. Strix Halo + 64GB RAM will beat a 4090 in any AI task if you scale it up sufficiently. And for local LLMs where capacity is by far the biggest bottleneck, it won't even be close.
Strix Halo directly competes for the semi-pro market that is buying 4090s instead of RTX 6000s. Significantly slower for tasks that fit inside 24GB, but can be used for tasks a 4090 can't touch.
This isn’t anything new, companies buy MacBooks with 128gb ram. They are incredibly popular because of this.Memory capacity is king. Strix Halo + 64GB RAM will beat a 4090 in any AI task if you scale it up sufficiently. And for local LLMs where capacity is by far the biggest bottleneck, it won't even be close.
Strix Halo directly competes for the semi-pro market that is buying 4090s instead of RTX 6000s. Significantly slower for tasks that fit inside 24GB, but can be used for tasks a 4090 can't touch.
no?Strix Halo will bring it the Windows world albeit with half the capacity of a M3 Max MacBook
That’s good. Last I saw an article that it’s up to 64 for halono?
8 ODPs amount of 128 gigs of DRAM for Halo.
before you say Mac isn’t a competitor.
You can get PHX/HWK laptops with 64 gigs L5X right now. lmao.That’s good. Last I saw an article that it’s up to 64 for halo
there's a good reason for that.still no solid leaks whatsoever
well stx1 RVP leaked, do the model off it idk.Where is my >30% st uplift?
BOOOOOOOOOOOOOO! SHAME HIM FOR NOT READING THE FORUMS ENOUGH!Wait wait wait, where did the talk of LP island/LP cores in Strix (Halo) IOD came from?
Was there some leak saying that that I missed or is this just some wild seronxposting? This feature was #1 on my wishlist (that or some advanced packaging chiplet tech that would not have power overhead)...
Because of regular bugs and unwanted/RDNA3 type of bugs? Pascal benchmarks were leaked a month before launch and it was a huge jump from Maxwell.there's a good reason for that.
well stx1 RVP leaked, do the model off it idk.
I'm sorry for asking the noob question but how do "additional transistors make you clock high" exactly?What they strip out might be the additional transistors that allows Zen 5 to clock high
Same question, different phrasing, what's a buffer cell? A register? Does having more clocks require more registers to deal with the extra throughput?The combined effect of reducing buffer cells due to a lower clock target + prolific use of a high density library should result in a very compact, power efficient core.
no.Because of regular bugs and unwanted/RDNA3 type of bugs?
how is this relevant to AMD?Pascal benchmarks were leaked a month before launch and it was a huge jump from Maxwell.
Ok we need to put a pin in this.Memory capacity is king. Strix Halo + 64GB RAM
For inference that's true. For training, different story.Strix Halo directly competes for the semi-pro market that is buying 4090s instead of RTX 6000s. Significantly slower for tasks that fit inside 24GB, but can be used for tasks a 4090 can't touch.
Ok we need to put a pin in this.
I THOUGHT Halo was 16Go.
Since a few days people say it's 32.
Now 64?
Are you all just randomly throwing darts at this or do we have any proper information?
There's a really solid leak that will drop in 459 hours.3 weeks to go, still no solid leaks whatsoever. Where is my >30% st uplift?
Yessiree! Not that I am counting either.There's a really solid leak that will drop in 459 hours.
Ok, 64Go could actually sell quite a lot to certain professional categories. And ML inference users too, ofc.16GB is the lowest you can go and still populate the entire interface using chips that are still in mass production. So that's a lower bound. Recently, someone noticed a bunch of shipping manifests for Strix Halo testing boards, some of which had 32GB and others had 64GB.
For inference that's true. For training, different story.
I'm sorry for asking the noob question but how do "additional transistors make you clock high" exactly?
Same question, different phrasing, what's a buffer cell? A register? Does having more clocks require more registers to deal with the extra throughput?
What's a high density library in this case?
L1D$ size does not fit, Zen 2 has 32KB.
At a cost of a bit of latency ?A buffer cell outputs the same signal as the input but in a faster/cleaner way. So, if a logic cell output has really slow rise/fall times that you need to improve, you can use a buffer cell to take the slow rise/fall time signal and make it into a fast rise/fall time signal. Area and power consumption is the trade-off.
Edit: I'm describing a simple digital logic buffer. There are other types of buffers as well.
L1D$ size does not fit, Zen 2 has 32KB.