8.Does that account for 4 of the cores being zen5c?
You're trying to model PPC out of HMP setup on a non-SIR workload.So were you wrong or what happened?
@adroc_thurston has never given us IPC numbers.Isn't 20% more IPC kinda low? You said something around 30-40 if I remember correctly? So were you wrong or what happened?
Just pointing out you're assuming the big and little cores are running at the same frequency, but I'd think it's pretty likely that won't be the case. More likely the cores will be limited by their power budgets instead, and they'll each hit the highest clocks they can within their respective power budgets.All those references are meaningless since TDP is unknown for all these parts excepted for the 7700X.
Using this CPU as reference and assuming that cores power is 125W then Strix Point has something like 20% better perf/clock if the run was made at 45W, this as an estimation based on power/frequency curves, assuming power scales at an average 2.8 power of frequency between 80 and 125W and 2.36 average between 45 and 80W.
FI computerbase measured the 7700X as 26% faster in Blender than a 7940HS at around 70-90W, their run over 100s display about 85W but Blender test last much more at 800s and they state that the CPU end running at 70W.
If we extrapolate from the Computerbase test, and using the 70W lower bound to not overestimate the calculation, then this Strix Point ES perform 26% better than a 7940HS@70W and about 52% better than a 7940HS@45W, so assuming a run at 45W that would make 1.52x the perf with 1.5x the core count, and this would also imply 20% better perf/clock.
Razer Blade 14 (2023) mit 7940HS und RTX 4070 im Test
Die 3. Generation Razer Blade 14 setzt auf AMD Phoenix und Nvidia Ada Lovelace. Statt 16:9 mit 144 Hz gibt es 16:10 mit 240 Hz. Der Test.www.computerbase.de
Did I miss something or the L3 and core clocks are now decoupled in Zen5?More likely the cores will be limited by their power budgets instead, and they'll each hit the highest clocks they can within their respective power budgets
Just pointing out you're assuming the big and little cores are running at the same frequency, but I'd think it's pretty likely that won't be the case. More likely the cores will be limited by their power budgets instead, and they'll each hit the highest clocks they can within their respective power budgets.
Thanks. So strix point is 4+8, kraken 4+4 and halo just flat out 16 ignoring the island? Or is kraken 2+4?8.
You're trying to model PPC out of HMP setup on a non-SIR workload.
Don't.
STX1 4+8Thanks. So strix point is 4+8, kraken 4+4 and halo just flat out 16 ignoring the island? Or is kraken 2+4?
What's Sonoma?
oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.the most efficient is to to distribute the frequencies evenly.
I think I understand this. For desktop and HEDT, its all about performance, so everything is Zen5 cores. For laptops, its all about power savings, and since Zen5c has all the same features, it could be 100% Zen5c cores. Servers, I would guess are all one or the other depending on what that specific chip is targeted at.oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.
If they didn’t then there’s no point of having “hybrid” cores. The point of having a P + c is c is much more efficient. One of reasons AMD did is to perform better at a lower TDP.oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.
No. Cost.For laptops, its all about power savings
It's just cheaper rofl.is c is much more efficient
Whichever way you slice it, 20% better perf per core is a "run of the mill" incremental update from AMD. It's nowhere near "Osborning everything before it" or if it were, Zen4 with its 30% ST perf uplift would have been a bigger dealYou're trying to model PPC out of HMP setup on a non-SIR workload.
Don't.
Man this is the worst attempt to own me in eons.Whichever way you slice it, 20% better perf per core is a "run of the mill" incremental update from AMD. It's nowhere near "Osborning everything before it" or if it were, Zen4 with its 30% ST perf uplift would have been a bigger deal.
PHX2 exists so no.Also is this the first time of P core and c core SoC from AMD in client?
SPEC INT vs FP.Isn't 20% more IPC kinda low? You said something around 30-40 if I remember correctly? So were you wrong or what happened?
oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.
We're talking Blender, not a particularly high overhead workload.Which, while theoretically possible, isn't generally the case either.
Your conclusion is based on that Blender result, right?Whichever way you slice it, 20% better perf per core is a "run of the mill" incremental update from AMD. It's nowhere near "Osborning everything before it" or if it were, Zen4 with its 30% ST perf uplift would have been a bigger deal
Isn't 20% more IPC kinda low? You said something around 30-40 if I remember correctly? So were you wrong or what happened?
oh hell no, Z5 and Z5c have very-very distinct v/f curves. Don't be silly.
Well there's two different L3s for each CCX, the main Zen 5 cluster has a 16MB L3, the Zen 5c cluster has an 8MB L3. So the L3 and core clocks don't need to be decoupled in the first place.Did I miss something or the L3 and core clocks are now decoupled in Zen5?
No the whole point of the C cores is to trim on area to just make them smaller, letting them for more of them in a smaller area and make more competitive products for the cloud market. Just like how V-Cache was designed for specific server workloads originally, then it was later realised it could be shipped on desktop as it happened to have a huge uplift on gaming, C cores were originally designed for cloud first, then later brought down to client products to improve competitiveness there as well.If they didn’t then there’s no point of having “hybrid” cores. The point of having a P + c is c is much more efficient. One of reasons AMD did is to perform better at a lower TDP.
Is this just a guess or is there some slide or whatever that confirms this?Well there's two different L3s for each CCX, the main Zen 5 cluster has a 16MB L3, the Zen 5c cluster has an 8MB L3