Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[igor_kavinski]

AMD Ryzen "Strix Point" APU matches Ryzen 7 7700X in leaked Blender tests - VideoCardz.com

AMD Strix Point as fast as Ryzen 7 7700X A new leak featuring a mobile processor with Zen5 architecture puts it just about higher than desktop Zen4 CPUs. The AMD Engineering Sample 100-000000994-38 isn’t new to VideoCardz users. We already covered this sample last month when it leaked onto the...

videocardz.com

4 Z5 + 8 Z5c cores against Alder Lake mobile 6P+8E looking darn good, especially if it doesn't exceed the 45W power envelope whereas Intel cheats with a 115W Turbo Power limit for the 12900H. And this sample has to be running at below final clocks. Exciting!!!

 

[eek2121]

AMD Ryzen "Strix Point" APU matches Ryzen 7 7700X in leaked Blender tests - VideoCardz.com

AMD Strix Point as fast as Ryzen 7 7700X A new leak featuring a mobile processor with Zen5 architecture puts it just about higher than desktop Zen4 CPUs. The AMD Engineering Sample 100-000000994-38 isn’t new to VideoCardz users. We already covered this sample last month when it leaked onto the...

videocardz.com

4 Z5 + 8 Z5c cores against Alder Lake mobile 6P+8E looking darn good, especially if it doesn't exceed the 45W power envelope whereas Intel cheats with a 115W Turbo Power limit for the 12900H. And this sample has to be running at below final clocks. Exciting!!!

IMO the mobile Zen 5 parts are looking pretty magical. I am definitely going to be upgrading at some point, though I will probably wait for Strix Halo.

 

[Saylick]

IMO the mobile Zen 5 parts are looking pretty magical. I am definitely going to be upgrading at some point, though I will probably wait for Strix Halo.

Speaking of STH... From Olrak's Twitter account (not linking to the tweet because it contains profanity):


Not much we already don't know, but good to see it visually.

 

[adroc_thurston]

Speaking of STH... From Olrak's Twitter account (not linking to the tweet because it contains profanity):
View attachment 99143

Not much we already don't know, but good to see it visually.

small brain couldn't even label USRs properly.
goddamit.

 

[HurleyBird]

Unless we've learned something different, the only precedent that AMD has established for combining their P cores and their C cores on the same die, Phoenix2, has a unified L3 for them both.

And Zen5c chiplets supposedly feature a 16-core CCX. Hard to imagine why Strix Point would have separate CCXs given both those points.

 

[adroc_thurston]

And Zen5c chiplets supposedly feature a 16-core CCX.

Yea.

Hard to imagine why Strix Point would have separate CCXs given both those points.

Because they serve very different purposes.

 

[PJVol]

Because they serve very different purposes.

Yeah, one is for computing, and the other is for calculations.

 

[HurleyBird]

Because they serve very different purposes.

I dunno, I'm struggling here. Big increase to die size and average core-core latency for a small improvement to intra-CCX latency seems like a bad trade. Doubly so when you only have 4 cores in the big core complex and games are standardizing around octocore.

Power gating? Maybe you can turn off one CCX entirely when it isn't needed? But with a smaller L3 you go out to main memory more often, and inter-CCX communication is more expensive.

The usual answer to these things when it comes to AMD is a combo of bet hedging and time-to-market.

 

[Tuna-Fish]

Because they serve very different purposes.

To be very clear, if Strix has two separate L3 caches, it will perform significantly worse on many important loads than if it has a single cache with 12 cores attached to it.

 

[Joe NYC]

To be very clear, if Strix has two separate L3 caches, it will perform significantly worse on many important loads than if it has a single cache with 12 cores attached to it.

Couple of problems with that:
- adding 4 stops on the ring bus would slow down all other addresses
- If L3 runs at core frequency, all cores would have to be on the same clock speed (which would be a deal-breaker of the Zen 5c cores)

 

[Gideon]

Couple of problems with that:
- adding 4 stops on the ring bus would slow down all other addresses
- If L3 runs at core frequency, all cores would have to be on the same clock speed (which would be a deal-breaker of the Zen 5c cores)

Well, the latter should already be a solved problem on Phoenix 2? Presumably it runs at the speed of the fastest core

 

[Joe NYC]

Well, the latter should already be a solved problem on Phoenix 2? Presumably it runs at the speed of the fastest core

We will see Turin D CCD has a ring bus with 16+ stops or if there is some sort of enhanced ring bus that Adored TV speculated on earlier...

 

[HurleyBird]

- adding 4 stops on the ring bus would slow down all other addresses

What ring bus? When the 8-core CCX debuted with Zen 3, iirc there was an interview stating that the new CCX was neither fully point-to-point nor a ring bus. If it were just a ringbus, adding more cores would be a much less involved process.

Edit: Can't corroborate my memory. Am I misremembering this??

 

[adroc_thurston]

To be very clear, if Strix has two separate L3 caches, it will perform significantly worse on many important loads than if it has a single cache with 12 cores attached to it.

Naaa.
It's a quad-core with a tumor on the side.
Relevant loads will fit into the premium quad, and cinememe/low power ghetto stuff will do fine on dense CCX.

If it were just a ringbus, adding more cores would be a much less involved process.

Please I beg you read the 2022 ISSCC Zen3 presentation.

We will see Turin D CCD has a ring bus with 16+ stops or if there is some sort of enhanced ring bus that Adored TV speculated on earlier...

Neither.

 

[itsmydamnation]

 

[DrMrLordX]

It's a quad-core with a tumor on the side.

Arnold reminds us that

It's not a tumor!

 

[PJVol]

What ring bus?

Spoiler

 

[Fjodor2001]

So what do we make of these upcoming AMD CPUs with a combination of Zen + ZenC + ZenLP cores? Is AMD not only going big.LITTLE but big-middle-little? Like these from ARM:

big.LITTLE

Arm big.LITTLE technology is a heterogeneous processing architecture that uses two types of processor.

www.arm.com

Example:
Armv9.2 - DynamIQ big.LITTLE - DynamIQ Shared Units-120 (up to 3 types of cores)
Ultimate-Performance CPU (CXC): Cortex-X4
Performance-Efficient CPU (big): Cortex-A720
High-Efficiency CPU (LITTLE): Cortex-A520

Where roughly:
X4 = Zen
A720=ZenC
A520=ZenLP

 

[Fjodor2001]

View attachment 99180

Only 16 days left until Computex.

But I wonder how much info we'll get at the announcement. Hopefully at least SKUs, pricing, core configs, frequencies, availability date, and some indication of average IPC improvement. Also mentioning of "new" stuff like NPU, AI CPU instructions, IOD (even though likely the same as Zen4), ...

However usually there'll be a 4-6 week review embargo after the announcement. And reviews, detailed benchmarks, etc are needed to fully evaluate Zen5. So likely we'll have plenty of time to continue speculating even after Computex.

 

[igor_kavinski]

I hope it's not "And last but not the least, here is a video of Zen 5 running a game at 6 GHz" and presentation end!

 

[Kaffeekenan]

I hope it's not "And last but not the least, here is a video of Zen 5 running a game at 6 GHz" and presentation end!

Would not mind it if it's "here is a game running at 6 GHz and 40% more IPC than Zen4".

 

[IEC]

Would not mind it if it's "here is a game running at 6 GHz and 40% more IPC than Zen4".

That's setting yourself up for disappointment.

I don't expect both a 40% IPC gain (already very high) and a fMax boost in the same generation. If they manage to pull a rabbit out of a hat and complete a magic trick to do that, Zen 5 will be unobtanium.

 

[dhruvdh]

This is the official description -

> AI is driving a revolution that is rapidly reshaping every aspect of computing and the technology industry. Dr. Lisa Su will explore how AMD, together with its partners, is pushing the limits in AI and high-performance computing from the data center, to the edge and end user devices.

It looks like it starts with the data center and ends at client. They might do a summary keynote and then separately a deep dive for the media. I think they did something similar for RDNA 3.

 

[Tuna-Fish]

I hope it's not "And last but not the least, here is a video of Zen 5 running a game at 6 GHz" and presentation end!

The more I think about it, the more I'm convinced that they are not going to launch both Zen5 and RDNA4 in the same event. Having two separate events is just better for them, if only because it means more press visibility.

So I think that the big event is all Zen5, in various different forms, and then the end teaser is RDNA4.

 

[Goop_reformed]

That's setting yourself up for disappointment.

I don't expect both a 40% IPC gain (already very high) and a fMax boost in the same generation. If they manage to pull a rabbit out of a hat and complete a magic trick to do that, Zen 5 will be unobtanium.

My father's friend's cousin's ex-wife's brother said it's gonna be 25%, and the gaming performance will be superb.