🤣I find it HIGHLY unlikely that AMD is going to drop EPYC Zen 6 full core count down to 96 cores.
I also find it IMPOSSIBLE to believe that AMD will reduce the core count on their EPYC dense. The entire purpose of the dense version is for cloud computing that doesn't utilize the L3 very well and where max core count rules.
I am thinking this is a little too far off the side of reason as well.
It's just my speculation at this time, but I find it much more likely that AMD will lean into chiplets and IOD technology in the next generations of processors. This will lead to smaller die sizes and more complex combinations of IOD's.
This gives AMD the best combination of cost reduction and scalability.
I believe a 32c CCD is technically possible, but it may well be economically inferior. Think of it this way....
AMD can EITHER create fewer VERY expensive CCD's and have a less complex packaging having fewer IOD's OR they can create MORE less expensive CCDs and use more IOD's.
I see no down side to the scaleable approach and many advantages.
Scaling via an IOD that has 4 channel memory allows AMD to scale memory channels along with processor cores keeping the system in balance.
Each generation AMD gets to decide what memory technology they will support the platform on, select the number of cores in a CCD that can be fed from that memory, then create an IOD that matches the number of channels needed to the number of CCD's supported.
Scaling of cores then becomes something that is only limited by the socket power and max memory channels supported by the socket design.
These kinds of decisions are my daily bread and butter. From a business standpoint, this looks pretty appealing to me.
I even doubt that there is a performance hit by putting fewer cores on a CCD and having more IOD's vs having fewer IOD's and having more cores on the CCD as work is scheduled by thread in the OS.
It's fine if you make $20 bln extra, people are happy to pay for the best stuff.So that $50.00 you are making such a small matter of translates into 5 billion dollars.
Until what exactly? And how certain are you? I thought Zen 6 was more of an end of 26 product.~15 months left....
H2 26 doesn't always mean July it means month in the range [7,12].~15 months left....
Something wrong is with your counting: 15 months from now is August not July.H2 26 doesn't always mean July it means month in the range [7,12].
For Intel it means 31 Dec 2026...H2 26 doesn't always mean July it means month in the range [7,12].
Ironically that's still meeting timelineFor Intel it means 31 Dec 2026...
oh yeah my bad lol but the range is right also MI400 is N2 as well.Something wrong is with your counting: 15 months from now is August not July.
It is if they actually do what they said they will - ship stuff in volume rather than token samples to legally meet their public timeline.Ironically that's still meeting timeline
Every semi product takes few months to be ramped in volume from launch.It is if they actually do what they said they will - ship stuff in volume rather than token samples to legally meet their public timeline.
It's not looking good.ehhh around summer/fall we'll have some numbers for sure
AMD/TSMC already has them but well hidden...
I find it HIGHLY unlikely that AMD is going to drop EPYC Zen 6 full core count down to 96 cores.
I also find it IMPOSSIBLE to believe that AMD will reduce the core count on their EPYC dense.
Goop reformed's takesWhat is not looking good?
SP5 power limit is around 500W I believe. The new SP7 expected for EPYC Zen 6 is going to be around 1000W.
It isn't reasonable to expect core counts to go DOWN from Turin models to Zen 6 models. I don't care what rumor you are parroting.
Additonally, having only bumped memory speeds from 6000MT to 6400MT means that they will absolutely need more IOD's. The rumor is up to 16 memory channels. Each IOD has 4 channels so that would mean 4 IOD's.
4 IOD's each having 4 CCD's will be the max config for BOTH EPYC standard (Zen 6) and EPYC Dense (Zen 6c) configurations. The difference will be in the number of cores on the CCD.
Someone feel free to knock holes in this line of argument.
It isn't going down? SP6 -> SP8 is 64->96 cores, SP5->SP7 is 192->256 cores.SP5 power limit is around 500W I believe. The new SP7 expected for EPYC Zen 6 is going to be around 1000W.
It isn't reasonable to expect core counts to go DOWN from Turin models to Zen 6 models. I don't care what rumor you are parroting.
Additonally, having only bumped memory speeds from 6000MT to 6400MT means that they will absolutely need more IOD's. The rumor is up to 16 memory channels. Each IOD has 4 channels so that would mean 4 IOD's.
4 IOD's each having 4 CCD's will be the max config for BOTH EPYC standard (Zen 6) and EPYC Dense (Zen 6c) configurations. The difference will be in the number of cores on the CCD.
Someone feel free to knock holes in this line of argument.
It isn't going down? SP6 -> SP8 is 64->96 cores, SP5->SP7 is 192->256 cores.
very simple.I am getting completely confused.
Sorano too.SP6 was the Siena platform, lower cost, socket used for "dense only" CCDs.
It also has dense and networking options.Is the successor to Siena, SP8 now full core, 8x12 = 96 cores?
very simple.
Sorano too.
It also has dense and networking options.
SP8 is their catchall ms server platform.
tl;dr they have more server share and thus can afford running more server platforms concurrently
Not relevant.Do the SP7 and SP8 support the same number of CCDs
It's just halves.IODs?
Here is the breakdown of Venice SP7 and SP8:I am getting completely confused. IIRC, SP6 was the Siena platform, lower cost, socket used for "dense only" CCDs.
Is the successor to Siena, SP8 now full core, 8x12 = 96 cores? If SP8 were to continue the "dense only" approach, it would use the 32 core CCDs, and 3 CCDs seems (in fact is) an odd number.
that's... made up? why are you confident in N3 for 12C classic? why is there a random jump from HP to HD in 192->256? reduce+reuse is like the whole motto of chiplets.Here is the breakdown of Venice SP7 and SP8:
- SP8: 96-core (N3P, 8x12-core, 384MB) + 1 IOD 8-channel
- SP8: 128-core HP (N2, 4x32-core, 512MB) + 1 IOD 8-channel
- SP7: 192-core HP (N2, 6x32-core, 768MB) + 2 IOD 16-channel
- SP7: 256-core HD (N2, 8x32-core, 1024MB) + 2 IOD 16-channel