Question Zen 6 Speculation Thread

[Tigerick]

that's... made up? why are you confident in N3 for 12C classic? why is there a random jump from HP to HD in 192->256? reduce+reuse is like the whole motto of chiplets.

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process. Plus my source told me long time ago.

HP and HD are same die just different power TDP. Some of the power analysis are based on my calculation in AMD ARM threads. Not confirm but pretty sure...

 

[Joe NYC]

Here is the breakdown of Venice SP7 and SP8:

1. SP8: 96-core (N3P, 8x12-core, 384MB) + 1 IOD 8-channel
2. SP8: 128-core HP (N2, 4x32-core, 512MB) + 1 IOD 8-channel
3. SP7: 192-core HP (N2, 6x32-core, 768MB) + 2 IOD 16-channel
4. SP7: 256-core HD (N2, 8x32-core, 1024MB) + 2 IOD 16-channel

The N3P 12 core highly unlikely

And the number of CCDs, memory channels and IODs has no consistency.

 

[adroc_thurston]

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process

?

 

[511]

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process. Plus my source told me long time ago.

AMD Publicly said Venice is N2

 

[jpiniero]

AMD Publicly said Venice is N2

Which is why the rumors that client doesn't use the server die anymore sounds about right.

 

[Tigerick]

AMD Publicly said Venice is N2

Yep, since both 8x12 or 3x32 will net total 96 cores, I am putting both options. If using 32-core, we might not get high boost clock, so..

 

[LightningZ71]

You're forgetting that there are "die recovery options" where they use dice that have one or more failed cores. 4 x 24 enabled core die works for 96 core products. I just don't expect to see that.

 

[fastandfurious6]

AMD Publicly said Venice is N2

referring to the joint TSMC-AMD press release?

they wouldn't specify N2X in that case, they probably mean N2-node-family