Question Zen 6 Speculation Thread

[inquiss]

AMD employs people who are paid very big $$$ to predict the future, every big company got 'em.

I mean, yeah. What's your point?

 

[marees]

AMD employs people who are paid very big $$$ to predict the future, every big company got 'em.

No one could have predicted memory fiasco from Samsung. AMD was smart to use more commonly available memory

Chip making is like a Russian roulette with the bullet hitting you after a delay of months & years

Having said that I would have released 9060xt last july. FSR 4 doesn't make a big difference in that market segment, imo

 

[Win2012R2]

I mean, yeah. What's your point?

The point is that when we have characters like MLID getting some info, the people working for AMD should have gotten x1000 level of info a LOT earlier.

No one could have predicted memory fiasco from Samsung.

Do you mean HBM?

AMD made smart choice to use GDDR6, that's for sure.

 

[Thunder 57]

AMD employs people who are paid very big $$$ to predict the future, every big company got 'em.



They should have bloody counted on it! Sooner or later Nvidia was bound to slip up and focus on AI was clearly indicating they are very likely to neglect consumer side.

Guess they should be hiring you then with your amazing hindsight abiaility. /s

 

[Win2012R2]

Guess they should be hiring you then with your amazing hindsight abiaility. /s

They should be promoting internal people who advocated for more forceful GPU approach - including making big Navi 4 and firing those who were against that.

 

[adroc_thurston]

AMD employs people who are paid very big $$$ to predict the future, every big company got 'em.

You don't expect your comp to screw up.

They should have bloody counted on it

Counted on NV just not executing?

Sooner or later Nvidia was bound to slip up and focus on AI was clearly indicating they are very likely to neglect consumer side.

AMD hates client GFX even harder than Nvidia.

They should be promoting internal people who advocated for more forceful GPU approach

They indeed have it, in GPGPU space.

and firing those who were against that.

I don't think firing Lisa Su is a good idea.

 

[Win2012R2]

I don't think firing Lisa Su is a good idea.

She should take responsibility for the stupid decision she made, fire those who advised her to not support that idea.

You don't expect your comp to screw up.

Nvidia was bound to fail at some point - they should have looked for signs of that and be prepared, it's their job!

AMD hates client GFX even harder than Nvidia.

It's a big market that can be very profitable if scale is achieved.

 

[adroc_thurston]

She should take responsibility for the stupid decision she made

It's a very smart decision. Client gfx is a low margin ghetto.

fire those who advised her to not support that idea.

Why would they fire good execs?

Nvidia was bound to fail at some point

You never bet on that.

they should have looked for signs of that and be prepared, it's their job!

lol

 

[Win2012R2]

Why would they fire good execs?

Because they are crap execs? They are likely missed one in a lifetime opportunity to turn the tide.

You never bet on that.

You watch for signs and prepare, it was their chance and they failed to take full advantage of it.

 

[adroc_thurston]

Because they are crap execs?

Lol.
Very smart people, they've built an amazing GPGPU roadmap.

They are likely missed one in a lifetime opportunity to turn the tide.

There is no opportunity to turn any tide.
Client gfx is a lost market to AMD.

You watch for signs and prepare, it was their chance and they failed to take full advantage of it

There never were any signs.

 

[Thunder 57]

They should be promoting internal people who advocated for more forceful GPU approach - including making big Navi 4 and firing those who were against that.

Fire people for making a mistake and not seeing the future. Genius! Who would want to work for a company like that?

Because they are crap execs? They are likely missed one in a lifetime opportunity to turn the tide.


You watch for signs and prepare, it was their chance and they failed to take full advantage of it.

Once in a lifetime? Nvidia has screwed up with FX, Fermi, and now the 5000 series. That's three so far in my lifetime and I'm far from an old man.

EDIT

I just realized we are in a Zen 6 thread. How did we get here?

 

[poke01]

l would rather the AMD consumer dGPU deparment die than fire Lisa.

An excellent CEO is rare these days and a women at that too. Keep her, AMD will need her and her skills.

For AMD's board they give zero shits about dGPU and its all about AI, Mx line and server cpus.

 

[Joe NYC]

There was a lot of discussion here, in the Zen 6 thread, about likelihood (inevitability) of moving to all 3D design, where the base CCD is a stacked die.

We had the usual Cassandra's talking about cost, packaging capacity why it can't be done (as if TSMC did not specialize in overcoming these obstacles).

Now, according to the latest MLID leak, it is in fact happening with Zen 7. Base CCD chip will be 3D stacked dies. Tom said caches are moving to a separate die - not sure if L3 but also L2. I would think that if L3 moves completely to a separate die, and perhaps runs at lower clock speed, then L2 can expand on the same dies as cores - but we will see.

It could even be top die being cores, middle die being L2 and bottom die(s) being L3, which would allow AMD to move to 16 core CCD, while staying at the same die sizes.

BTW, good episode to watch, because he has one of my favorite guests, Max from High Yield.

 

[511]

There was a lot of discussion here, in the Zen 6 thread, about likelihood (inevitability) of moving to all 3D design, where the base CCD is a stacked die.

We had the usual Cassandra's talking about cost, packaging capacity why it can't be done (as if TSMC did not specialize in overcoming these obstacles).

Now, according to the latest MLID leak, it is in fact happening with Zen 7. Base CCD chip will be 3D stacked dies. Tom said caches are moving to a separate die - not sure if L3 but also L2. I would think that if L3 moves completely to a separate die, and perhaps runs at lower clock speed, then L2 can expand on the same dies as cores - but we will see.

It could even be top die being cores, middle die being L2 and bottom die(s) being L3, which would allow AMD to move to 16 core CCD, while staying at the same die sizes.

BTW, good episode to watch, because he has one of my favorite guests, Max from High Yield.

I watched and had normal MLID annoyances like he said somewhere Launching 2027 it is not launching before 2028 with DDR6 His launch date should never be taken seriously 🤣.

The only reason I watched it was High Yield and AMD is already doing this with MI300 afaik and Intel with Clearwater Forest.

 

[yuri69]

Tom said caches are moving to a separate die - not sure if L3 but also L2.

IMO adding a few cycles of load-to-use from stacking is OK for L3, not so much for L2. So...

 

[adroc_thurston]

not so much for L2

+4 cycles but 4 times the capacity would be alright.

 

[511]

+4 cycles but 4 times the capacity would be alright.

Intel is already doing +3 Cycles but 3 times the capacity but less bandwidth.

 

[adroc_thurston]

Intel is already doing +3 Cycles but 3 times the capacity but less bandwidth.

Indeed.
Just that RKL-S to RPL-S was like 4 times the L2 at 4 cycle penalty.
AMD can do the same.

 

[Joe NYC]

I watched and had normal MLID annoyances like he said somewhere Launching 2027 it is not launching before 2028 with DDR6 His launch date should never be taken seriously 🤣.

The only reason I watched it was High Yield and AMD is already doing this with MI300 afaik and Intel with Clearwater Forest.

I would not be paying attention to any release estimates from that video, just the technology talk.

 

[Joe NYC]

+4 cycles but 4 times the capacity would be alright.

The stacked chip with caches could also have the ring bus / mesh.

The latencies could reshuffle as a result. L2, for example, could be closer to the cores (just below), which could offset the +4 cycles.

Then, if both L2 and L3 are on the same die, there would not be any increment to L3 latency, being on the same die as the ring bus.

Removing both L2 and L3, going to next process node, and even going from 12 to 16 cores could still result in main core die being smaller than Zen 6. Or, the transistor count could of each core could grow substantially.

 

[511]

I am not expecting SRAM Shrink before CFETs. CFETs are promised to 2X SRAM Density.

 

[Hulk]

Is this like nuclear fusion 🤔

Cold fusion, so better.

 

[soresu]

Saying you explained it, and then immediately reasoning that AMD should have known the future... if only they could have reasoned it the way you did, it was so obvious...with your current knowledge...of the present.

Blackwells specs are very decent. You'd expect more performance, something went wrong. AMD could not have known they'd produce a dud, or not produce enough etc. They couldn't... unless of course they could see the future, like you.

It's not mystical prognostication in business when you base your line of reasoning on what a company has done in any given situation in the past as well as what they are doing in the present.

Did you think that no one in this industry (or business in general) uses past trends to inform strategy?

The actions of nVidia are both cliche and predictable for a market leader, or anyone in a position of power for a significant length of time.

It's not exactly a new concept. the ancient Greeks even had a word for it.

We've seen very similar moves from Intel in the past when they thought their position unassailable.

While this is very entertaining to discuss we do seem to have drifted somewhat off topic for Zen 6 speculation, so if you want to continue then @ me from either an AMD or nVidia thread in the gfx sub forum.

 

[soresu]

it's possible the Dense Zen6 parts will be able to match all core frequency of Zen5 non-dense parts

Perhaps if the 6c parts are 'double pumping' AVX512 execution, but in general the dense parts are designed for that feature to the exclusion of per core perf gains.

If we are really talking a full doubling of CCD density then I would expect minimal clock gains barring some nice µArch improvements in the clock efficiency area on top of fixed errata from any Zen5 legacy circuits.

The latter being something I think might have the most potential given how much Zen5 was hyped by AMD, only to fall somewhat below expectation when it came to launch - unless they pushed some of Zen5's µArch design to Zen6 for time reasons, something I recall being said about Zen1 -> Zen2 being better than expected in IPC due to deferred Zen1 µArch features ending up in Zen2.

 

[adroc_thurston]

The latencies could reshuffle as a result. L2, for example, could be closer to the cores (just below), which could offset the +4 cycles

Distance like, doesn't impact cache perf like that.