Question Zen 6 Speculation Thread

[marees]

Back in late 2018, Vega 20 was the first chip to come out along with a couple of phone socs on N7, which was as big of a jump as N2 is supposed to be. I don't understand why some people keep repeating the same old talking points, that N2 is too expensive bla bla, as if they actually know any hard data point.

That was Raja Koduri
This is Lisa Su

 

[Schmide]

Back in late 2018, Vega 20 was the first chip to come out along with a couple of phone socs on N7, which was as big of a jump as N2 is supposed to be. I don't understand why some people keep repeating the same old talking points, that N2 is too expensive bla bla, as if they actually know any hard data point.

Just ordered a couple Instinct MI50s for $110 each to play with their double precision (6.705 TFLOPS (1:2))

 

[reaperrr3]

That was Raja Koduri
This is Lisa Su

She was just as much CEO back then as she is now and wouldn't have approved that choice unless they considered it a net positive.
Besides, they had already skipped 10nm by that point, and the energy and clock benefits of N7 were huge.

Vega20 was also of relatively modest size (compared to Vega10 and Volta), plus it wouldn't have had any competitive edge whatsoever without the fastest process available.
The fact that it reached such high clocks at all, with not that many CUs disabled either, indicates the yield rate can't have been that bad.

They did delay Navi10 a bit due to yield reasons, but that was a new architecture and a GPU for mainstream graphics cards selling for <400$, where every $ margin (and every additional month of driver work) counted.

In any case, I don't think AMD would choose N2 unless yield curve as well as electrical and density benefits looked promising enough for the wafer price increase.

 

[Thibsie]

Well AFAIR, Zen5 was supposed to be N3(B). N3B failure made them port it to N4P.

So N4P wasn't a conservative choice at all, just fallback. The argument against N2 for Zen6 just falls to oblivion IMO.

 

[Joe NYC]

Hard to say if this is the right thread to continue, but...
Computerbase reports that mainboard makers told them at Computex that CUDIMM support is coming, presumably with a new cIOD. Which datarates will be supported then is not yet fixed.

If there is a new IO chips (for Zen 5) wouldn't it make sense for it to Strix Halo packaging and Strix Halo CCDs?

Assuming the Strix Halo CPU can support V-Cache as well.

 

[Joe NYC]

- Zen6 will be a H2 (probably Q4) product, since N2 HVM only starts in H2

N2 HVM starts in H2 2025

 

[StefanR5R]

If there is a new IO chips (for Zen 5) wouldn't it make sense for it to Strix Halo packaging and Strix Halo CCDs?

Computerbase wrote "The next CPU generation presumably gets a new IOD, and with it a memory controller which supports CUDIMMs" [fully, not just in bypass mode]. It is not clear to me what "the next CPU generation" which the mainboard makers alluded to actually was.

My guess is that Strix Halo will remain the only Zen 5 product which is moved to fanout. This CUDIMM support might be Zen 6, or an upcoming Zen 5 AM5 APU, or Granite Ridge but with refreshed IOD and switched to GMI wide mode. (Narrow doesn't make much sense combined with CUDIMM speeds.) Somehow a Granite Ridge refresh seems unlikely to me, and Zen 6 seems still further away than for mainboard makers having a loose tongue about one of its features at Computex now... so, maybe a Strix Point based desktop APU? (That is, enhanced IMC yes, but not exactly in the form of an IOD.)

 

[LightningZ71]

From what we are hearing, Zen 6 MUST have a new IOD as compared to Zen 5 DT. Assuming that it's true, then it must have full CUDIMM support natively to stay market relevant. I would also assume such for low end desktop and desktop APUs of the Zen6 generation.

 

[Joe NYC]

Computerbase wrote "The next CPU generation presumably gets a new IOD, and with it a memory controller which supports CUDIMMs" [fully, not just in bypass mode]. It is not clear to me what "the next CPU generation" which the mainboard makers alluded to actually was.

My guess is that Strix Halo will remain the only Zen 5 product which is moved to fanout. This CUDIMM support might be Zen 6, or an upcoming Zen 5 AM5 APU, or Granite Ridge but with refreshed IOD and switched to GMI wide mode. (Narrow doesn't make much sense combined with CUDIMM speeds.) Somehow a Granite Ridge refresh seems unlikely to me, and Zen 6 seems still further away than for mainboard makers having a loose tongue about one of its features at Computex now... so, maybe a Strix Point based desktop APU? (That is, enhanced IMC yes, but not exactly in the form of an IOD.)

If the Strix Halo interface (to IOD) is compatible with Zen 6 interface (not necessarily the case, just saying "what if"), then AMD could de-risk Zen 6 launch and have a mid-gen upgrade for Zen 5 by releasing Zen 5 (Strix Halo CCD) with this new IOD ahead of Zen 6 launch.

Some of the features of such an upgraded CPU with upgraded IOD could be:
- support for faster memories
- lower internal latency
- IOD could add 50 TOPs NPU
- IOD could move to RDNA 3.5

The big item missing would be LP cores. But is it my imagination or did MLID say that LP cores on future AMD processors may be Zen 5? Or perhaps AMD might skip LP cores on desktop IODs.

 

[LightningZ71]

Maybe Zen5c_mobile. Anything more is a waste for that purpose. Though, it MUST keep up with the P cores for instruction compatibility, so it's either going to gain a microcode block/area, or it's going to have to get a few Xtor tweaks to add the missing instructions along the way.

 

[adroc_thurston]

If the Strix Halo interface (to IOD) is compatible with Zen 6 interface (not necessarily the case, just saying "what if"), then AMD could de-risk Zen 6 launch and have a mid-gen upgrade for Zen 5 by releasing Zen 5 (Strix Halo CCD) with this new IOD ahead of Zen 6 launch.

this would be epically omega true but CPU tile tapes out first. bad news!

 

[StefanR5R]

If the Strix Halo interface (to IOD) is compatible with Zen 6 interface (not necessarily the case, just saying "what if"), then AMD could de-risk Zen 6 launch and have a mid-gen upgrade for Zen 5 by releasing Zen 5 (Strix Halo CCD) with this new IOD ahead of Zen 6 launch.

Each of Strix Halo's CCDs is attached with 32 Bytes read per cycle/ 32 Bytes per cycle write to its IOD (source).
Strix Point's CCXs also go with 32/32 B each to the IMC (source).
Granite Ridge: 32 Bytes/ 16 Bytes per cycle read/ write per CCD (source).

Turin's CCDs have 32/32"16+B" *but* times two in SKUs which use GMI3-Wide (source; my understanding is that Turin SKUs with up to 64 cores = up to 8 CCDs use GMI3-Wide instead of -Narrow; edit: AMD's slide says SKUs with up to 8 CCDs can use -Wide, and the write path is not 32B wide but 16...25B per link).

Thus, both Strix Halo and Strix Point, if moved into a CUDIMM supporting desktop CPU or APU, would only have a small advantage in terms of CPU memory access bandwidth over current Granite Ridge without CUDIMM support.

 

[burninatortech4]

From what we are hearing, Zen 6 MUST have a new IOD as compared to Zen 5 DT. Assuming that it's true, then it must have full CUDIMM support natively to stay market relevant. I would also assume such for low end desktop and desktop APUs of the Zen6 generation.

I don't see anyway that Zen 6 DOESN'T have a new IOD. In addition to the rumored LP cores (I'll believe that when I see it).

RDNA 3.5 iGPU, CUDIMM support, improved DDR5 memory controller, improved USB high speed support, and much more.