Thats pure rumor, and its 99% hogwash. Zen5C IS N3 and was always planned to be. Zen 5 was always going to be N5 or N4. To do otherwise would be to break AMDs cadence since the beginning of Zen:Well AFAIR, Zen5 was supposed to be N3(B). N3B failure made them port it to N4P.
So N4P wasn't a conservative choice at all, just fallback. The argument against N2 for Zen6 just falls to oblivion IMO.
Lol what so TSMC screwed over Intel 🤣 cause you need to know these things in advanced but I doubt it. It can be that 5C was supposed to be N3B and than stuff happened and they moved it to 3E.Well AFAIR, Zen5 was supposed to be N3(B). N3B failure made them port it to N4P.
So N4P wasn't a conservative choice at all, just fallback. The argument against N2 for Zen6 just falls to oblivion IMO.
You still need retimers for both starting next year Intel is getting rid of retimers and PD everything is getting integrated into SoC with Nova Lake 🤣.On-die USB4 would be nice so we can stop wasting x4 pcie 5.0 lanes for an x2 pcie 4.0 USB4 controller.
I want my two dedicated cpu m.2 slots back.
It was all N3.It can be that 5C was supposed to be N3B and than stuff happened and they moved it to 3E.
LMAO so Intel got screwed with the og N3B Prepay 🤣.It was all N3.
Not really, they got a better node in the end.LMAO so Intel got screwed with the og N3B Prepay 🤣.
I wouldn't call it a better node considering they got 6 months of delay with the worst cost structure in N3 Family anyway AMD Dodged a bullet here.Not really, they got a better node in the end.
It is a better node.I wouldn't call it a better node considering they got 6 months of delay with the worst cost structure in N3 Family anyway AMD Dodged a bullet here.
vs N4P no it's not much efficient it is a sizeable increase in density though.It is a better node.
Much denser and a sizeable chunk more efficient.
It is much more efficent at most 1v and below.vs N4P no it's not much efficient it is a sizeable increase in density though.
see the DTCO part?ok so all i could find is N5 vs N3B missing N4P but it would be rather close to N3 than to N5.
It certainly got them deeper into the red faster than ANY other process available on Earth at that time.Not really, they got a better node in the end.
that's because they have competitively lower margins and have to run a fab roadmap while not using them much atm.It certainly got them deeper into the red faster than ANY other process available on Earth at that time.
Yeah they did, Zen2 and Zen4 benefited massively from TSM process shrinks.None of these great advances from AMD had much to do with lithography shrinks IMO.
I'm sure they planned all along to have negative margins and that the 20bn cost of 18A had nothing to do with it.that's because they have competitively lower margins and have to run a fab roadmap while not using them much atm.
AMD benefited massively from abandoning the mantra "Real Men Have Fabs". Intel would be wise to abandon it as well ..... albeit now seems a little too late.Yeah they did, Zen2 and Zen4 benefited massively from TSM process shrinks.
Honestly your fuhrerbunker rants are kinda weird. Like you don't get it.
So we're heading towards TSMC monopoly, with China<->Taiwan war risk included in the deal, and no second source.AMD benefited massively from abandoning the mantra "Real Men Have Fabs". Intel would be wise to abandon it as well
Because they will and they did before 3nm went bad. If only the were a link. A link, a link, my kingdom for a link.Also,
Client
Zen 2,3 ->7nm Node
Zen 4,5 ->5nm Node
Why do you believe that AMD will now suddenly change?
YES.I'm sure they planned all along to have negative margins and that the 20bn cost of 18A had nothing to do with it.
Nope. Design teams at Intel are free to use whatever's the best tool for the job.I'm sure that paying out the nose for N3B also had nothing to do with it.
They do use the most expensive process and the most Si where it matters (like GPGPU).AMD is ALSO benefiting from a PROFITABLE business model that does not rely on using the most expensive process and having the largest die size on the market
none of that was an issue, they just couldn't execute well.AMD wasn't always so smart though. They also once thought to profit through lithography and vertical integration. Yea, we all know how that went. AMD didn't have the volume or the resources to make a competitive vertical integrated model work. Neither does Intel.
Because Zen5 was all N3 until N3 got late.Why do you believe that AMD will now suddenly change?
Taiwan doesnt really matter. In 5 years, Chinas SMIC will have caught up and/or surpassed TSMC. Mark those words.So we're heading towards TSMC monopoly, with China<->Taiwan war risk included in the deal, and no second source.
LmaoIn 5 years, Chinas SMIC will have caught up and/or surpassed TSMC
That attitude is exactly why when it happens, ignorant people in the west will be shocked and bewildered. Chinas manufacturing arm is already the most advanced on the planet, and by a long shot. They will apply the same laser focus and direction of the last 10 years to the next 10 for AI and semiconductor production. You think they just shat out an AI solution that already competes with Blackwell because they "got lucky"? Do you think you know better than Huang himself? Huawei is a force to be reckoned with, with the full backing of the CCP.Lmao
Huawei's technology, based on our best understanding at the moment, is probably comparable to an H200.
They've been moving quite fast. They've also offered this new system called Cloud Matrix, which scales up to even a larger system than our latest generation, Grace Blackwell. Huawei, as you know, is a formidable technology company. And they're not sitting still.
They look for ways to compete, and they're quite formidable.
- Jen-Hsun Huang
The funny thing is if Zen5 was supposed to be on 3nm