Question Zen 6 Speculation Thread

[511]

Nope but necessary evil IMO.
In 3-5 years, they should come with real nice designs. Or they will fall.

in 1.5 years lol Nova Lake and DMR are very good especially Halo NVL.

 

[Fjodor2001]

Someone can correct me but I'm interpreting the comments on desktop being based on mobile as like mobile high end and desktop merging in how they look and function.

Do you mean as in sharing the same dies?

Also, to be more concrete what SKUs are we talking about. E.g. successor to 9950X on desktop will merge with successor to ??? on mobile/laptop, or is it some other SKUs you’re talking about?

And what does this mean in practice. E.g. that desktop will get beefier iGPU inherited from mobile/laptop on Zen6, and/or something else?

 

[adroc_thurston]

And what does this mean in practice

Means it a luggable-first part with proper mobile uncore and power management.

that desktop will get beefier iGPU inherited from mobile/laptop on Zen6

Luggable parts have no beefy iGP on any vendor.

 

[511]

Do you mean as in sharing the same dies?

Also, to be more concrete what SKUs are we talking about. E.g. successor to 9950X on desktop will merge with successor to ??? on mobile/laptop, or is it some other SKUs you’re talking about?

And what does this mean in practice. E.g. that desktop will get beefier iGPU inherited from mobile/laptop on Zen6, and/or something else?

I think it will be like the 12C CCX will be universally(Mobile Desktop Server as well) shared than there will be the IOD on N4C with LP-E cores for Desktop and maybe server will get a different one cause the 4C die will contain LP-E cores and Die Waste Unit.
Mobile die is N3P for cheaper SKUs and than they will add 12C with the N3P for oomph.
Zen6 halo will be seperate.

Same with Nova Lake there is 4+0/4+8/8+16/8+16 big LLC die and than there is unified SoC for all with 4 LP-E cores shared across mobile and Desktop.

Tht's what i think it will turn out

 

[Thibsie]

in 1.5 years lol Nova Lake and DMR are very good especially Halo NVL.

I hope for their sake

 

[Fjodor2001]

I think it will be like the 12C CCX will be universally(Mobile Desktop Server as well) shared than there will be the IOD on N4C with LP-E cores for Desktop and maybe server will get a different one cause the 4C die will contain LP-E cores and Die Waste Unit.
Mobile die is N3P for cheaper SKUs and than they will add 12C with the N3P for oomph.
Zen6 halo will be seperate.

Not sure if I’m missing something, but in essence this only means desktop & mobile will get a different (and common) IOD than server on Zen6. No more dramatic change than that compared to Zen5 w.r.t. ”desktop being based on mobile instead of server on Zen6”?

 

[511]

Not sure if I’m missing something, but in essence this only means desktop & mobile will get a different (and common) IOD than server on Zen6. No more dramatic change than that compared to Zen5 w.r.t. ”desktop being based on mobile instead of server on Zen6”?

desktop mobile and server will have different IOD yes.

 

[adroc_thurston]

No more dramatic change than that compared to Zen5 w.r.t. ”desktop being based on mobile instead of server on Zen6”?

It's completely different uncore with completely different power management for luggable and DT parts.

 

[Fjodor2001]

desktop mobile and server will have different IOD yes.

So that’s all there is to it w.r.t. the ”desktop being based on mobile instead of server on Zen6”? No more dramatic changes than that compared to Zen5 in that regard?

 

[Fjodor2001]

It's completely different uncore with completely different power management for luggable and DT parts.

Ok, but is all of that contained in the IOD, so no major changes elsewhere with regards to this?

 

[adroc_thurston]

so no major changes elsewhere?

D2D and power delivery are also different.
It's a mobile workstation part.

 

[StefanR5R]

Are die-to-die interfaces going to differ between SP7 and SP8 too?

 

[Fjodor2001]

So I assume that one of the ideas with having a different IOD for desktop/mobile on Zen6 is to lower the power consumption in idle, and in low performance scenarios (reading web page, typing email, watching video, etc).

Only the 4 LPE cores and iGPU are hopefully needed then, so the performance cores do not have to be fired up. I.e. the stuff on the IOD alone will suffice.

But I wonder how well it'll work in practice. I found this Reddit post discussing how it works on Intel Arrow Lake H:

https://www.reddit.com/r/intel/comments/1kkpn6x/what_do_lpe_cores_actually_do_in_practice

which says:

"in all the situations Ive tracked: 100% idle laptop with no apps, simple browsing, watching youtube, and even rendering workloads, the LPE cores are 90% of the time parked, with the P and E cores having light utilization."

So it does not seem to work as intended. Could the reason be that Windows does not (yet?) handle the LPE cores that well, or do those cores have too little performance so they're not even able to handle the use cases quoted above on their own? There is a response comment suggesting it's the latter:

"For an example of LP-E working very well, see Lunar Lake. 4x Skymont is plenty fast enough to keep tasks contained, while 2x Crestmont isnt. IMO, the LP-E cluster should have been a full 4x Crestmont to give it a fighting chance at working better."

So do we know what performance can be expected from the Zen6 LPE cores on the desktop/mobile IOD? Will they be sufficient for handling low performance tasks as mentioned above without having to wake up the performance cores?

 

[StefanR5R]

The low power cores are not for interactive workloads. They are for "modern standby" and perhaps other background bloat.

 

[511]

The low power cores are not for interactive workloads. They are for "modern standby" and perhaps other background bloat.

That was the case for Meteor Lake and ARL-H in case of LNL they are quite capable and actually and keep even light web browsing/excel on the LP-E cores.

 

[StefanR5R]

An SP7 liquid cooler was displayed at Computex:
https://www.servethehome.com/auras-...d-plate-for-600w-cpus-shown-at-computex-2025/

Seems as if the length stays the same as of SP5 coolers, but the width is a little bit increased (by less than 10%).

 

[OneEng2]

Because Intel.

I agree that this is the wild card. It seems to me that AMD would have to have already placed their bets on a process node for each die by this time though. Sure, it would be nice to know ahead of time if Intel were any threat or not, but I suspect AMD doesn't yet know (I doubt if Intel knows either ).

Now you're trolling....This is exactly what people have been saying in this thread. Desktop and server get N2 class and volume stuff uses N3 class.

What's changed here to make you now accept the reality of what's been written for several pages now?

I have always maintained that N2 will be used for server (at a minimum for Zen 6 Venice D). The question has always been what node will desktop and laptop use.

An interesting wrinkle that has been brought into the argument is monolithic vs chiplet. Personally, I would argue that monolithic is a better candidate for N3P than N2 specifically due to die size and yields (ie costs and run capacity issues).

Anything monolithic is getting N3 per this thread. Anything high end is using N2. So that means servers, desktop retail, threadripper I'm guessing. Someone can correct me but I'm interpreting the comments on desktop being based on mobile as like mobile high end and desktop merging in how they look and function.

The node choice makes sense to me. When AMD launched on TSMC on 7nm they only had that on a good node. Now with the high end on N2, mainstream on N3 and legacy stuff on N4 they have access to many more options for volume. Where Intel has had a stranglehold on OEM I expect a big part of that OEM angle has been the volume they can provide. With each gen AMD is adding mass and options on nodes to draw from, so much IP on each node to mix and match that I expect OEM deals to become more likely.

I would argue that because your last statement is likely true (AMD breaking into OEM in a meaningful way), that mobile will likely be on N3P to lower costs.

My contention is (and has always been) that N2 will be reserved for low volume, high margin parts. I also think it is possible that N3P may actually yield higher max clock speeds than N2 (until later iterations of N2) making N3P a natural selection for desktop.

I think it will be like the 12C CCX will be universally(Mobile Desktop Server as well) shared than there will be the IOD on N4C with LP-E cores for Desktop and maybe server will get a different one cause the 4C die will contain LP-E cores and Die Waste Unit.
Mobile die is N3P for cheaper SKUs and than they will add 12C with the N3P for oomph.
Zen6 halo will be seperate.

Same with Nova Lake there is 4+0/4+8/8+16/8+16 big LLC die and than there is unified SoC for all with 4 LP-E cores shared across mobile and Desktop.

Tht's what i think it will turn out

It's as good a guess as any here has had. So your guess is that AMD will minimize the number of die variations they create and sell it across multiple segments.

Seems like we have the following rationale in this thread:

1. Maximize performance at any cost (except at the value segment)
2. Maximize profit (my bet) by using the most expensive processes only on high profit, low volume parts.
3. Minimize engineering effort by re-using die across multiple channels.

My opinions at this time:

1) It's a fairy tale that we want to believe.
2) It's in-line with AMD's previous business practices and makes the most sense from a financial perspective
3) This assumes that AMD is potentially resource constrained and doesn't want to go through as many designs to cover all market variation. This also my include the rationale that volume of scale is important for a die for financial reasons and production capacity flexibility across markets.

I think #1 will only happen if AMD has actionable evidence showing that they can't compete without the best node on nearly all parts for Zen 6. Hard for me to believe right now.

#2 is likely because it is what AMD has been doing.

#3 is likely because if the assumptions are correct, it best fits AMD's business and engineering resource limitation needs.

 

[Timmah!]

So any news on Zen6 recently, the desktop parts i mean? Havent paid attention recently at all, dont even know whether there was Computex already.

 

[OneEng2]

So any news on Zen6 recently, the desktop parts i mean? Havent paid attention recently at all, dont even know whether there was Computex already.

The only meaningful information I can recall is that one or more of the server parts will be the first off the TSMC N2 line.

Leaks suggest that a new IOD for server will be modular and support 4 CCDs and 4 channels of memory. Since socket SP7 only supports 16 channels, speculation about core counts revolves around a max of 4 IOD's and 16 CCD's for DC.

I don't recall much leakage of information on laptop or desktop.

 

[inquiss]

I agree that this is the wild card. It seems to me that AMD would have to have already placed their bets on a process node for each die by this time though. Sure, it would be nice to know ahead of time if Intel were any threat or not, but I suspect AMD doesn't yet know (I doubt if Intel knows either ).

I have always maintained that N2 will be used for server (at a minimum for Zen 6 Venice D). The question has always been what node will desktop and laptop use.

An interesting wrinkle that has been brought into the argument is monolithic vs chiplet. Personally, I would argue that monolithic is a better candidate for N3P than N2 specifically due to die size and yields (ie costs and run capacity issues).

I would argue that because your last statement is likely true (AMD breaking into OEM in a meaningful way), that mobile will likely be on N3P to lower costs.

My contention is (and has always been) that N2 will be reserved for low volume, high margin parts. I also think it is possible that N3P may actually yield higher max clock speeds than N2 (until later iterations of N2) making N3P a natural selection for desktop.

It's as good a guess as any here has had. So your guess is that AMD will minimize the number of die variations they create and sell it across multiple segments.

Seems like we have the following rationale in this thread:

1. Maximize performance at any cost (except at the value segment)
2. Maximize profit (my bet) by using the most expensive processes only on high profit, low volume parts.
3. Minimize engineering effort by re-using die across multiple channels.

My opinions at this time:

1) It's a fairy tale that we want to believe.
2) It's in-line with AMD's previous business practices and makes the most sense from a financial perspective
3) This assumes that AMD is potentially resource constrained and doesn't want to go through as many designs to cover all market variation. This also my include the rationale that volume of scale is important for a die for financial reasons and production capacity flexibility across markets.

I think #1 will only happen if AMD has actionable evidence showing that they can't compete without the best node on nearly all parts for Zen 6. Hard for me to believe right now.

#2 is likely because it is what AMD has been doing.

#3 is likely because if the assumptions are correct, it best fits AMD's business and engineering resource limitation needs.

You're so close, almost there.

1) Use N2 where performance matters most. Server (both types of cores)
Desktop and luggable (where chiplets are used) and probably halo CPU

2) Use N3 where you need volumes and it's more cost sensitive.
Laptop APUs.

3)Use older nodes where cost is the biggest factor
IODs
Still selling zen 5 as low cost desktop and legacy mobile products

There might be some other nodes used. I don't know what happened to Sonoma valley or if there is a replacement for that on the roadmap.

Maybe some iod dies are in (2) as well

 

[Doug S]

Seems like we have the following rationale in this thread:

1. Maximize performance at any cost (except at the value segment)
2. Maximize profit (my bet) by using the most expensive processes only on high profit, low volume parts.
3. Minimize engineering effort by re-using die across multiple channels.

I agree 100%. Always bet on profit maximization. Even when the result is better performance the underlying goal is profit maximization - you can charge more for better performance. This is why Intel took their foot off the gas when AMD was lost in the Bulldozer wilderness. Their only competition was their own last generation products, so better performance beyond "just enough so you can see some daylight between the new and previous generation" did not meaningfully increase revenue so it wasn't worth effort to do better than "just enough".

 

[OneEng2]

I agree 100%. Always bet on profit maximization. Even when the result is better performance the underlying goal is profit maximization - you can charge more for better performance. This is why Intel took their foot off the gas when AMD was lost in the Bulldozer wilderness. Their only competition was their own last generation products, so better performance beyond "just enough so you can see some daylight between the new and previous generation" did not meaningfully increase revenue so it wasn't worth effort to do better than "just enough".

Great example. Counter example was leading up to P4 where Intel pushed its production clear up to the point where the 1Ghz PIII could only be produced in miniscule quantities in the face of the Athlon onslaught.

So the biggest question seems to be, is Intel's architecture broken fundamentally (as Bulldozer was), or can a quick fix free the architecture to breath better?

It almost seems like roles have been reversed and that Intel is going for the "more cores" crown while AMD is placing its bets on "everything else that runs fine on 24c/48t or less"

Of course, with a very few exceptions, Zen 5 bests Arrow Lake on multithreaded workloads (the most notable being CB24).

One could easily see AMD laying back and absorbing profits while Intel flounders with the ARL architecture for a full generation.

Panther Lake should give us some idea. It is sticking with Skymont for its E cores, but moving up to Cougar Cove for P cores. We are sneaking up on H2 2025 so I would expect to start seeing some leakage if the roadmap is to be believed.

Another factor (other than Intel) is if we believe that AMD will architect its Zen 6 with an eye primarily toward Server, then trickle down the tech and make due with it on client applications. AMD has been pretty solid on not making a design for each market (other than die combinations).

AMD seems to be gaining market share hand over fist in DC where the profits are very high. I am betting they continue this march and design Zen 6 for DC. It might even be that AMD gives up the high performance desktop (other than gaming) and laptop for DC margins. If Zen 6 breaks into the OEM business in a big way (due to price/performance) and DC feeds the profit machine, this seems like a pretty decent strategy.

This is not to say that I believe Nova Lake is going to best Zen 6 on desktop (certainly not in gaming), but I believe it to be possible as the latency on ARL is soooo bad at this time that freeing up that bottleneck could yield some potent IPC increases IMO.

My point is that AMD could decide to lose to Nova Lake for client in the interest of profit. After all, if AMD holds out long enough and remains profitable, Intel might take itself out of the game. An Intel without fabrication might well take a round or two of design to get its ducks back in a row (as an example).

 

[marees]

Maybe relevant to the discussion we are having on zen 6 nodes

Only top customers can afford it! TSMC's process price is expected to reach $45,000, and these big manufacturers are scrambling to buy it​

Chip manufacturers are gradually entering the 2nm process, and the price of each chip has risen to $30,000​

The supply chain revealed that the total cost for a chip factory to build a 2nm chip from project inception to output is as high as US$725 million (approximately NT$21.6 billion). TSMC's 2nm wafer foundry price has soared to US$30,000 (approximately NT$900,000) per piece, and Angstrom's process is said to reach US$45,000 (NT$1.34 million). In the future, only top customers can afford it, confirming the arrival of the chip Warring States era!

頂端客戶才玩得起！台積埃製程定價上看4.5萬美元 這些大廠瘋搶

台積電2奈米晶片客戶盤點台積電2奈米即將投產，一線客戶除AMD，聯發科宣布Tape-out（設計定案）倒數，蘋果、高通明年手機旗艦級晶片將接棒採用。供應鏈透露，晶片廠打造2奈米晶片，從開案到產出總成本高達7.25億美元（約新台幣216億元），台積電2奈米晶圓代工價格每片飆升至3萬美元（約新台幣90萬...

www-ctee-com-tw.translate.goog

https://twitter.com/x/status/1929329790055772454

 

[basix]

These cost numbers are ridiclously high. In my opinion much too high. I feel that these so called "analysts" just spread these numbers to get attention.

 

[511]

Maybe relevant to the discussion we are having on zen 6 nodes

Only top customers can afford it! TSMC's process price is expected to reach $45,000, and these big manufacturers are scrambling to buy it​

Chip manufacturers are gradually entering the 2nm process, and the price of each chip has risen to $30,000​

The supply chain revealed that the total cost for a chip factory to build a 2nm chip from project inception to output is as high as US$725 million (approximately NT$21.6 billion). TSMC's 2nm wafer foundry price has soared to US$30,000 (approximately NT$900,000) per piece, and Angstrom's process is said to reach US$45,000 (NT$1.34 million). In the future, only top customers can afford it, confirming the arrival of the chip Warring States era!

頂端客戶才玩得起！台積埃製程定價上看4.5萬美元 這些大廠瘋搶

台積電2奈米晶片客戶盤點台積電2奈米即將投產，一線客戶除AMD，聯發科宣布Tape-out（設計定案）倒數，蘋果、高通明年手機旗艦級晶片將接棒採用。供應鏈透露，晶片廠打造2奈米晶片，從開案到產出總成本高達7.25億美元（約新台幣216億元），台積電2奈米晶圓代工價格每片飆升至3萬美元（約新台幣90萬...

www-ctee-com-tw.translate.goog

https://twitter.com/x/status/1929329790055772454

Bruh the translation is not good I think he meant $725 Million to tape out a chip on 2nm process technology.
For 30K Wafer Price it is 1.5X increase vs N3E for a 15-20% PPA Improvements lets say TSMC charges relatively more due to being a Monopoly maybe 25% more it would be still 25K Wafer assuming N3E is 20K Wafer.