Question Zen 6 Speculation Thread

[Tigerick]

You said no DDR6 / LPDDR6 before 2028.

Part of the problem with that statement is mixing LPDDR6 and DDR6. LPDDR6 is its own thing, for mobile phones. High volume production is supposed to start before the end of 2025. Customers are phone OEMS. Phone SoC makers will support it very soon.

Which means, LPDDR6 will already be in the phones from 2026. So I don't see how price and availability would push a higher end product (high end laptop) 2 years after the phones.

As far as no new product before 2028, again, that's mixing DDR6 into the mix, which is a separate thing, for servers and desktops, not for Medusa Halo

Yep. @511 LPDDR6 and DDR6 have different timelines. Samsung has mentioned below:

The roadmap calls for yearly DDR5 speed upgrades of up to 8800Mbps by the year 2027 with 9600Mbps DDR6 projected to be available by the year of 2028 with even higher speed rates.

As for LPDDR6....according to Korean article here:

The vice chairman of the Samsung DS division is expected to develop the next-generation LPDDR6 using the 1c DRAM process in the second half of this year and supply it to big tech companies such as Qualcomm, repelling China's pursuit.

We could see Qualcomm X Elite G2 to utilize LPDDR6 end of this year.

 

[basix]

For desktop Zen 6 they will definitely stick to DDR5 (and AM5). Medusa Point might get LPDDR6 Support, but if they downsize the iGPU to 8CU anyways, LPDDR5(X) will be fine. Especially, if they would use more bandwidth efficient RDNA4/5 architectures.

But for Medusa Halo LPDDR6 would make much sense. Either you hamstring the iGPU due to lack of bandwidth, or add Infinity Cache with respective amounts or use LPDDR6. Timelines won't be an issue, as Medusa Point will release last in the Zen 6 family in late 2026 ore even 2027 (one post above: LPDDR6 will be used this year already). Cost could be an issue, but volumes of LPDDR6 will be high by end of 2026, but so will probably be demand (smartphones, Apple, datacenter?). Nevertheless, Medusa Halo is a premium product with respective price tags. So cost ist not a too big issue as well. And then the first new kid on the block: ML/AI. Bandwidth matters very much there. And I suspect, LPDDR6 comes with higher memory capacities as well. And the other two kids around: Apple Mx APUs and now Nvidia/Mediatek N1X. Without LPDDR6 you either have no edge or you even fall behind.

 

[StefanR5R]

Memory latency and bandwidth are dependent variables of one another. […]
https://mahmoudhatem.wordpress.com/2017/11/07/memory-bandwidth-vs-latency-response-curve/
View attachment 125290

Graphs like this depend a lot on the specific hardware, and the specific test workload. (The article makes it sound as if there is a universal "40%/80% law", but there is not. Not remotely.) However, one rule is universal: DRAM technology sets the horizontal latency bar beneath which whatever implementation-dependent latency-bandwidth curve cannot go.

But virtually independent of how such latency-bandwidth response characteristics of a given hardware system look in detail, if you have a homogeneous workload running, the workload can in the end be characterized as either latency-bound or bandwidth bound. How latency gradually changes between low and high bandwidth utilization is not important to real but homogeneous workloads.

Things get interesting however if you have a concurrent mix of a latency sensitive workload with a bandwidth hogging workload. Then, QoS policies/safeguards which are implemented in the hardware become highly important. Example:
https://chipsandcheese.com/p/pushing-amds-infinity-fabric-to-its
As is highlighted in this article, AMD improved latency from Ryzen 7950X(3D) to 9950X a lot in certain edge cases of heterogeneous workloads. I wonder if perhaps AMD's development work for Strix Halo (two Zen 5 CCXs paired with a bandwidth loving extralarge iGPU)¹ fed back into Granite Ridge, in this regard.

[Edit, apropos large APU: ¹) After AMD got MI300A's fabric and memory subsystem working, Strix Halo's must have been a piece of cake for them.]

 

[bearmoo]

So let me get this straight, the Qualcomm/Mediateks will be making N3 SoCs and pair them with LPDDR6, while on the pc side we will have N2 chips but can't afford the memory? Do people just imagine their fantasies/bias to be facts?

 

[adroc_thurston]

So let me get this straight, the Qualcomm/Mediateks will be making N3 SoCs and pair them with LPDDR6, while on the pc side we will have N2 chips but can't afford the memory? Do people just imagine their fantasies/bias to be facts?

Phones live in a PoP ghetto. MoB or CAMM formats for LPDDR6 will be awhile later.

 

[poke01]

Phones live in a PoP ghetto

Apple is moving to WMCM next year for phones, don’t know about the Android space though.

 

[adroc_thurston]

will x3d zen6 launch

yeah why not lmao.

Apple is moving WMCM next year for phones

That's still InFO.

 

[poke01]

yeah why not lmao.

Was a typo but might as well ask will it launch same time as normal zen6?

 

[igor_kavinski]

will it launch same time as normal zen6?

I don't think that's possible with the hard limit on production capacity they have for the X3D chips. They could probably increase production at greater cost but they prefer to take their time to build up stock with their existing manufacturing/validation capacity.

 

[adroc_thurston]

Was a typo but might as well ask will it launch same time as normal zen6?

I dunno.

I don't think that's possible with the hard limit on production capacity they have for the X3D chips

No it's a product-level decision.

 

[Saylick]

Lisa just confirmed Venice is on 2nm at their AI event today.

 

[DisEnchantment]

Current reveal from advancing AI

1.27x perf/core * 1.33x more cores = 1.7x perf gain?

 

[jpiniero]

1.27x perf/core * 1.33x more cores = 1.7x perf gain?

Sounds about right. The 9965 is already 500 W tho... and even though N2P's power savings is good, 500 W is pushing it.

 

[adroc_thurston]

Sounds about right. The 9965 is already 500 W tho... and even though N2P's power savings is good, 500 W is pushing it.

Venice (well, SP7 one) is 600W, but it's also much much higher membw.

 

[BorisTheBlade82]

Venice (well, SP7 one) is 600W, but it's also much much higher membw.

That's around 3x of EPYC Turin, isn't it?
What kind of RAM and how many Channels will they be using?

 

[Io Magnesso]

The 256 core version is probably the Zen6c version of Venice?
I was surprised because it is rare to introduce such a large number of cores to an AI server.
Well, it's not confirmed whether it's actually equipped with Zen6 or whether it's equipped with Zen6c.

 

[jpiniero]

That's around 3x of EPYC Turin, isn't it?
What kind of RAM and how many Channels will they be using?

The regular Turin has a 500 W model too (9755)

 

[Markfw]

That's around 3x of EPYC Turin, isn't it?
What kind of RAM and how many Channels will they be using?

The 9555 (64 core) I think is 360 watt. I should look it up... Yup, see below

The AMD EPYC 9555 is a 64-core processor with a base clock speed of 3.2 GHz and a maximum turbo frequency of 4.4 GHz. It has a 256MB L3 cache and a TDP of 360W. It supports DDR5-6400 memory and has 128 lanes of PCIe Gen5. The 9555 is part of the 5th generation AMD EPYC Turin series.

 

[BorisTheBlade82]

@Everyone
I meant RAM BW, not TDP. Sorry - thought that was obvious.

 

[BorisTheBlade82]

The 256 core version is probably the Zen6c version of Venice?
I was surprised because it is rare to introduce such a large number of cores to an AI server.
Well, it's not confirmed whether it's actually equipped with Zen6 or whether it's equipped with Zen6c.

Must be, as 256/12 (c Venice CCD) would be 21.3 CCD 🤷🏽‍♂️

 

[Gideon]

Venice (well, SP7 one) is 600W, but it's also much much higher membw.

I wonder what allows that extra bandwidth.

Looking at the specification timeline, it's probably DDR6.

I just don't see another way to double the bandwidth (as they claim). Even with CAMM potentially allowing extra memory channels , near 2x sounds a bit optimistic on DDR5

 

[BorisTheBlade82]

To keep per core RAM BW constant, they would need a 128 GByte/s D2D interface BW compared to 64 GByte/s GMI narrow. To keep RAM BW : CCD BW of roughly 10:1 constant, they would need around 170 GByte/s.
That should obviously be the range for Desktop Venice too, finally allowing it to use all the RAM BW provided on a single CCD (and core).

 

[BorisTheBlade82]

I wonder what allows that extra bandwidth.

Looking at the specification timeline, it's probably DDR6.

I just don't see another way to double the bandwidth (as they claim). Even with CAMM potentially allowing extra memory channels , near 2x sounds a bit optimistic on DDR5

Yep, that interests me as well.
And they do not double, they almost triple. 1.6 TByte/s / 576 Gbyte/s = 2.77

 

[Abwx]

View attachment 125414

Current reveal from advancing AI

1.27x perf/core * 1.33x more cores = 1.7x perf gain?

That s not all, there s an update for this CPU as early as 2027.

AMDs HPC-AI-Roadmap: Instinct MI500 mit Epyc „Verano“ kommt bereits 2027

AMDs neue HPC-AI-Roadmap blickt zwei Jahre voraus. 2027 soll neben Instinct MI500 auch die siebte Generation Epyc erscheinen.

www.computerbase.de

 

[Kepler_L2]

I wonder what allows that extra bandwidth.

Looking at the specification timeline, it's probably DDR6.

I just don't see another way to double the bandwidth (as they claim). Even with CAMM potentially allowing extra memory channels , near 2x sounds a bit optimistic on DDR5

16-channel DDR5-12800 MRDIMM