Question Zen 6 Speculation Thread

[Io Magnesso]

Are all models equipped with V-cache?
That's a bit suspicious...
The cost of V-cache and the cost of post-processing (advanced packaging) are never cheap. It's good if you want the ultimate performance in the game Not all people are like that... For those who want to focus on cost performance, all models V-Cache as standard equipment is a nuisance that increases the cost in a sense…
On top of that, you can see the top model of HX, but the V-CACHE standard on the laptop is a concern for power consumption.

To be honest, I also want Zen6, so I'd like to try Ryzen Build for the first time...
It's hard to have V-cache installed on all models
That's a problem, because I'm not trying to pursue game performance to the limit.
I'd like it to be cheaper.
Well, it's about that MLID, so let's take it as a nonsense story.

 

[igor_kavinski]

One thing that could give Intel bLLC a massive edge (for me at least) would be if the bLLC is shared between BOTH compute tiles.

I know that's complicated and I really don't care how they do it but if they can, then wow at least I'll be pleased.

 

[Io Magnesso]

The more cash you have, the better… That's not to say (Although it's a good thing)
Of course, as the quantity increases, it becomes more difficult to manage…

 

[Io Magnesso]

One thing that could give Intel bLLC a massive edge (for me at least) would be if the bLLC is shared between BOTH compute tiles.

I know that's complicated and I really don't care how they do it but if they can, then wow at least I'll be pleased.

Even the NVL chiplet layout is not yet known at this time, so let's enjoy what's going on.

 

[poke01]

It’s just way too early to judge NVL

 

[Io Magnesso]

It’s just way too early to judge NVL

That's right, of course, ZEN6 (Olympic Ridge) too

 

[Joe NYC]

NVL-S 54C + bLLC for $700 (or somewhat above) sounds like a good deal

I have a feeling that the whole NVL will be "ass" as someone described it above.

If there was enough performance from 8P + 16E + bLLC to beat AMD Zen 6 V-Cache, Intel would sell just that and it would be a Halo product.

There would by no need to throw in 2nd tile. The need to throw in a 2nd tile is a strong indication that NVL will be another fail, not even close to being a Halo product.

And 2nd tile will be there just so that Intel can cling on to win in some irrelevant synthetic benchmark, as a morale booster for the few remaining hardcore Intel fans. The type who bought ARL motherboards a month before ARL benchmarks were released.

 

[Joe NYC]

One thing that could give Intel bLLC a massive edge (for me at least) would be if the bLLC is shared between BOTH compute tiles.

I know that's complicated and I really don't care how they do it but if they can, then wow at least I'll be pleased.

If the cache is shared (which the name misleadingly suggests), then its latency and gaming performance would be even worse.

 

[Fjodor2001]

If there was enough performance from 8P + 16E + bLLC to beat AMD Zen 6 V-Cache, Intel would sell just that and it would be a Halo product.

There would by no need to throw in 2nd tile. The need to throw in a 2nd tile is a strong indication that NVL will be another fail, not even close to being a Halo product.

NVL-S 8P+16E will not be sufficient to beat 24C Zen6, so Intel needs the 2nd tile which brings 52C (2 x 8P+16E + 4 LPE).

And 2nd tile will be there just so that Intel can cling on to win in some irrelevant synthetic benchmark, as a morale booster for the few remaining hardcore Intel fans.

It’ll be a win for Intel, and perhaps considered synthetic by the ST crowd, but not by those looking for MT perf. Depends on what use cases you have.

 

[Joe NYC]

NVL-S 8P+16E will not be sufficient to beat 24C Zen6, so Intel needs the 2nd tile which brings 52C (2 x 8P+16E + 4 LPE).

I think the key comparison will be:

Zen 6 12c vs. NVL 8P+16E
and
Zen 6 12c + V-Cache vs. NVL 8P+16E+bLLC

That is, if Intel offers a CPU with a single tile with bLLC. If Intel does not offer it, it will be a because Intel is losing that comparison with higher cost CPU. Which would be a sign of trouble that 2 tile, 52c NVL will not be able to overcome.

 

[DrMrLordX]

Yeah, unless Intel decides to go kamikaze and put a massive dent in AMD's gaming marketshare by pricing their bLLC chips too aggressively.

Intel doesn't have enough money to do that, and Lip Bu Tan's call for higher gross margins will prohibit them from future price-cutting. Unless he goes back on his plan for 50%+ gross margins.

There would by no need to throw in 2nd tile. The need to throw in a 2nd tile is a strong indication that NVL will be another fail, not even close to being a Halo product.

There's still the possibility that the 48c Nova Lake-S will be cancelled. It'll need to be priced really high to chase the margins Intel will want/need for it.

 

[adroc_thurston]

There's still the possibility that the 48c Nova Lake-S will be cancelled

Nnnope.

 

[igor_kavinski]

So seems Intel desperately wants to avoid the PR nightmare of not being able to match AMD's thread count...

 

[igor_kavinski]

It'll need to be priced really high to chase the margins Intel will want/need for it.

285K was priced above $1000 for the first month or two in the UAE. It came down only after sufficient stock arrived. It's now priced roughly $100 above 9800X3D.

 

[adroc_thurston]

So seems Intel desperately wants to avoid the PR nightmare of not being able to match AMD's thread count...

It's just a 2t NVL-S.
Boring.

 

[Kaffeekenan]

Pretty much everything.

Can you just name ONE thing? Like IPC? Clocks? Area?

 

[igor_kavinski]

If the cache is shared (which the name misleadingly suggests), then its latency and gaming performance would be even worse.

I'm assuming Intel would need that tile shared cache because

1) Zen 6 12C CCD will have access to 128MB L3 cache

2) Things get much worse for Intel if that 12C CCD has access to dual stacked 256MB L3 cache

In both scenarios, with bLLC connected to just one tile, Intel will have only 8 P-core threads with large cache access compared to 24 AMD threads accessing large L3 cache. Let's assume here that more than 8 threads on the Intel tile needing to use the E-cores is suboptimal for the game engine.

Now if Intel has that dual tile shared bLLC, now 16 P-core threads can work almost like they are on the same tile thanks to frequent data accesses from the shared bLLC. It may not end up being faster than AMD's design but it could mitigate the performance impact much better than the scenario of only 8 P-core threads with bLLC and 8 P-core threads on the other tile facing a larger cache deficit.

 

[igor_kavinski]

Zen 6 12c + V-Cache vs. NVL 8P+16E+bLLC

There's a good chance that AMD will increase the V-cache size to keep per thread cache availability consistent with the current X3D products. So that's minimum 192MB V-cache but then why stop there and why not just double it to 256MB and lift even more cache pressure off of the Zen 6 threads? If Intel can't put more than 144MB bLLC on its chips, then heavy cache using games are out for Intel for good. Their only respite may be using two 144MB bLLC, each connected to a tile. Very expensive for them.

 

[Tuna-Fish]

I'm assuming Intel would need that tile shared cache because

1) Zen 6 12C CCD will have access to 128MB L3 cache

2) Things get much worse for Intel if that 12C CCD has access to dual stacked 256MB L3 cache

144MB, 240MB if dual stacked. 48MB on die with the cores, 96MB per v-cache die.

 

[Joe NYC]

So seems Intel desperately wants to avoid the PR nightmare of not being able to match AMD's thread count...

I think Intel wants to avoid PR nightmare of not being able to match AMD at anything. So they release a Cinebench Special.

 

[poke01]

I have a feeling the 52 core part is a dual 445K part but with better bins.

I have a question to the folks knowledgeable with Nova lake, will it also double the iGPU, Media engines and I/O ie like the M3 Ultra OR is it just the CPU title getting doubled?

 

[poke01]

I think Intel wants to avoid PR nightmare of not being able to match AMD at anything. So they release a Cinebench Special.

Funny, cause the Zen6 24/48 core part will match or likely come very close to the 48/48 part.

Can you just name ONE thing? Like IPC? Clocks? Area?

Going by past information here, it won’t be as good at clocking as high as Zen6, IPC will be “good”, area of the P core will be bad relative to Zen6.

As for the IPC we don’t know but I wonder if going to 32 registers will help. Who knows

 

[Joe NYC]

I'm assuming Intel would need that tile shared cache because

1) Zen 6 12C CCD will have access to 128MB L3 cache
2) Things get much worse for Intel if that 12C CCD has access to dual stacked 256MB L3 cache

The most likely amounts are:
48 MB L3 with no V-Cache
144 MB L3 with 1 layer of V-Cache
240 MB L3 with 2 layers of V-Cache

In both scenarios, with bLLC connected to just one tile, Intel will have only 8 P-core threads with large cache access compared to 24 AMD threads accessing large L3 cache. Let's assume here that more than 8 threads on the Intel tile needing to use the E-cores is suboptimal for the game engine.

Interesting way to look at it, I did not think about it. AMD would have 24 threads on big cores vs. Intel's 8 threads on big cores.

Now if Intel has that dual tile shared bLLC, now 16 P-core threads can work almost like they are on the same tile thanks to frequent data accesses from the shared bLLC. It may not end up being faster than AMD's design but it could mitigate the performance impact much better than the scenario of only 8 P-core threads with bLLC and 8 P-core threads on the other tile facing a larger cache deficit.

In case of AMD, L3 is very tightly coupled with cores in the CCD, and has amazingly low latency. Latency only goes up slightly in V-Cache.

So a single thread, or first 8 threads, the latency could still be increased by having to share the L3 between tiles.

Shared L3 would have to have a completely new algorithms, several latency adders and final latency could end up 2x or 3x of AMD L3 latency. Maybe a very clever algorithm could cut this down, but not by a lot.

 

[adroc_thurston]

240 MB L3 with 2 layers of V-Cache

Not happening.

 

[Kepler_L2]

I have a feeling the 52 core part is a dual 445K part but with better bins.

I have a question to the folks knowledgeable with Nova lake, will it also double the iGPU, Media engines and I/O ie like the M3 Ultra OR is it just the CPU title getting doubled?

I think some of the I/O is doubled, but not iGPU/Media/Display.