Darkmont
Member
- Jul 7, 2023
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Definitely hallucination.BTW, I asked Grok and Grok answer (could be hallucination) for ballpark estimate was 10-15 ns for GMI link and 2-3 ns for Strix Halo type parallel link.
Definitely hallucination.BTW, I asked Grok and Grok answer (could be hallucination) for ballpark estimate was 10-15 ns for GMI link and 2-3 ns for Strix Halo type parallel link.
Definitely hallucination.
I doubt it. Lisa runs a tight ship with respect to making sure there's a business case for every investment and then to prioritize the products with the highest returns first. Regarding >1-Hi V-cache: they probably did some internal studies and the conclusion was that it offered little benefit relative to the cost. If the returns on investment weren't going to ever pan out, it never makes it out of the conceptual stage. That means no engineering samples, no real products, nada. It never sees the light of day, even as a "side quest".Maybe now, when AMD CPU division is cruising on its main quest, maybe Lisa will OK this side quest...
Earlier today Grok was repeatedly praising Hitler so I'm not sure if "hallucination" is even the right word for what it spews.
Oh, I thought Zen 6 was all about the uncore.That's the only thing you're really getting.
I doubt it. Lisa runs a tight ship with respect to making sure there's a business case for every investment and then to prioritize the products with the highest returns first. Regarding >1-Hi V-cache: they probably did some internal studies and the conclusion was that it offered little benefit relative to the cost. If the returns on investment weren't going to ever pan out, it never makes it out of the conceptual stage. That means no engineering samples, no real products, nada. It never sees the light of day, even as a "side quest".
Based on Adroc's comments, the same can be said for AMD not chasing the ultra high-end for discrete graphics. The type of customer for that bracket of desktop GPUs is not particularly price sensitive (read: not value conscious) and AMD simply doesn't have the branding nor position in the market to justify producing enough volume for such a product.
This the crux of it. I doubt the benefits of 2-High outweighs the costs, even if there's non-zero demand for it. In other words, the marginal profit to be made from selling two CPUs with 1-High V$ each are higher than selling one CPU with 2-High V$ + another without V$ at all.Imagine a hypothetical conversation:
AMD techie: we can make 2-hi V-Cache, and it will add 2% of performance
Lisa: How much will people pay for it?
AMD marketing guy: 10%
This the crux of it. I doubt the benefits of 2-High outweighs the costs, even if there's non-zero demand for it. In other words, the marginal profit to be made from selling two CPUs with 1-High V$ each are higher than selling one CPU with 2-High V$ + another without V$ at all.
Stacking more V$ dies on top of itself stresses the part of the manufacturing supply chain that is currently the bottleneck: advanced packaging. Wafers themselves aren't the bottleneck. Plus with more stacks, you're dealing with lower overall yields. Do the performance advantages of 2-High outweigh the costs, which include opportunity costs? Likely not, otherwise AMD would've done it.This is an argument from the scarcity POV, from a (assumed) necessity for tradeoff. But if you look at history of selling CPUs, probably 95% of the time, sales of CPUs are limited by demand and only about 5% of time, sales are limited by supply.
But a typical forum poster thinks it is the reverse.
If Lisa made a call to TSMC and said: "We need to double the number of N4P wafers for Zen 5 next quarter)
TSMC likely reply: "2x might be a little tight for next quarter, we can come close, but next quarter, no problem. Let us know if you want to go to 3x quarter after that".
So what is the argument if there is no tradeoff?
Nah. They are afraid it will be too popular and they won't be able to fulfill demand. Plus, it could eat into some of their Genoa-X and soon Shimada Peak-X profits.Likely not, otherwise AMD would've done it.
Stacking more V$ dies on top of itself stresses the part of the manufacturing supply chain that is currently the bottleneck: advanced packaging. Wafers themselves aren't the bottleneck. Plus with more stacks, you're dealing with lower overall yields. Do the performance advantages of 2-High outweigh the costs, which include opportunity costs? Likely not, otherwise AMD would've done it.
Nah. They are afraid it will be too popular and they won't be able to fulfill demand. Plus, it could eat into some of their Genoa-X and soon Shimada Peak-X profits.
Only invalid if you can offer concrete proof of its invalidityinvalid argument
yesGranite/Olympic Ridge compared to Raptor/Meteor/Arrow/Panther Lake?
Not really proof of AMD's paranoia that dual V-cache CCDs will be bad for them. If they considered it good, they would've done it already.The shortages are over,
Who cares.
People at AMD not gonna subject themselves to copious amounts of *redacted torture just to shave a few fabric ns for a bunch of forum dwellers. they have better stuff to do.
case. closed.
Not really proof of AMD's paranoia that dual V-cache CCDs will be bad for them. If they considered it good, they would've done it already.
That did not happen.
But apparently, Grok was dropping too many truth bombs. Which is its mission statement, after all.
Hard to reconcile search for truth and serving the most heavily propagandized population that prefers soothing lies to provocative truths.
You can literally google "grok praising Hitler" and see pages and pages of links to stories about it
2 layers X3D is like 2 X3D CCD.
Can they do it?
YES
Will they do it?
NO