This is exactly correct.No, this is not true in DC and laptop at all. It is true for desktop, and then really only for ST performance (and even then only for non-latency limited apps) as even high core count desktop is becoming power and thermal limited if not socket power limited. It is true that Intel has pursued a course like you suggest. I would say this is part of the reason why they are in such a bad state. Ironic since I thought they learned their lesson with P4 and Netburst, but alas.
Then what you want is better IPC and wider cores. but AMD will go for clocks as will everyone elseThis is why I'm not "wowed" by 6GHz or 6GHz+ clock speeds. I'm interested in what frequency can be sustained all-core with a heavy load, which is a "real life" situation encountered anytime you are multi-tasking.
I mean kinda not really.Then what you want is better IPC and wider cores.
anything goes really.but AMD will go for clocks as will everyone else
I'm just saying advertised max frequency is quite different from all-core fully loaded frequency. It's not a good or bad thing, just reality. I'm generally happy with every new generation of CPU I purchase. I'm a fan of the tech at the end of the day.Then what you want is better IPC and wider cores. but AMD will go for clocks as will everyone else
Pinning you down to facts and figures is like trying to pin a watermelon seed on a wet glass table with only one finger.Quite literally true for everyone and everything.
Go zoom is the meta.
It makes you wonder if they might make a couple of the cores with transistors designed for max frequency, and the rest of the cores with more power efficiency focus. As you point out, even in desktop, it is more about how much work you can do within the power envelope for the socket. I think this is even MORE relevant in DC.This is exactly correct.
Let's think about it for a minute because frequency has become quite nuanced over the past 5 or 10 years. It's not like a processor is rated at 3.9GHz and it does that regardless of the number of cores or workload (aka good old Sandy Bridge 2500K).
The 9950X is rated to "boost up to 5.7GHz."
Consider decent cooling, like an AIO, and stock 200W package power.
It will do 5.7GHz with 1 or 2 cores operating even under very heavy loads. But if you begins to load additional cores you will quickly consume those 200W and under a really heavy load may only see 4.9 or 5GHz (or less) with all cores loaded up. If you increase the power then without really good cooling you run into thermal issues.
So the real question is, what is the frequency with a certain amount of cores loaded running a certain workload?
I realize CB is not loved around here as a compute benchmark but perhaps it is a good benchmark for comparing "loaded" all-core frequency? For example, with a 280AIO my 9950X will run CB R23 at 4.7GHz resulting in a score of just under 41,000. That is consuming 200W. Obviously if you want to increase the power and have the cooling quite a bit of performance is available. My 13900K would score just under 36,000 at the same 200W. I think that is an apples-to-apples comparison. My 13900K would run 4.9GHz for the P's and 3.8GHz for the E's at 200W in CB R23. Stock-for-stock.
So, IMO the real question regarding Zen 6 isn't what is specified but what frequency it can do in comparison to the previous generation? This will be complicated if Zen 6 is indeed 24 cores because even at lower frequencies it will do well in MT apps like CB. If Zen 6 could achieve equal all-cores loaded frequencies with 24 cores as Zen 5 with 16 cores then that would be a huge performance win, but that also seems unlikely. But we shall see.
This is why I'm not "wowed" by 6GHz or 6GHz+ clock speeds. I'm interested in what frequency can be sustained all-core with a heavy load, which is a "real life" situation encountered anytime you are multi-tasking.
Overdrive nodes very very very explicitly trade leakage characteristics for going zoom zoom.First, can we agree that designing a transistor to optimize max frequency means that it CAN'T also be designed for maximum power efficiency?
Not at all, AMD in particular loves abusing the living hell out of their DVFS implementation.as it is rare that all cores go to max boost speed?
Well, without the fin-flex of later nodes, AMD tested those waters a bit with Strix Point. It's an OK product that looks like it wanted a later node. Intel has been doing that in the U/P power level market since Alder Lake with a 2+8 processor that seems to work really well for general office type use. Having a few cores that heavily optimize for 1T performance with a bunch of smaller, supporting cores for nT performance seems to be a good solution for much of the market.It makes you wonder if they might make a couple of the cores with transistors designed for max frequency, and the rest of the cores with more power efficiency focus. As you point out, even in desktop, it is more about how much work you can do within the power envelope for the socket. I think this is even MORE relevant in DC.
Aside from power, you also need to feed the beast. You can only feed so many cores with a dual memory configuration before you start to starve the cores. The latest news from Zen 6 seems to imply that quite a bit of changes are coming to Zen 6 with respect to bandwidth (and possibly latency) of memory. Makes me think things may look quite different in CB24 come 2026 .
It may well be that power efficiency becomes the biggest design issue moving forward (if it isn't already) and max frequency is simply something that becomes nearly static over the next decade.
I dunno about that.M1>M4 1T gains are ~80% clocks, it is absolutely a big trend to scale performance gen on gen until a harder frequency wall is hit, which will require CFET to surpass.
I can't read(too small a print), can you summarize please.For anyone still wondering about the mesh vs ring thing, see the top right of the screen shot. Literally top line, right hand column.
View attachment 122452
WOW, that sounds like wonderful improvements. Looking forward to Zen 6.
Just clearing up this is already in Zen5WOW, that sounds like wonderful improvements. Looking forward to Zen 6.
AMD does not describe Zen5 L3 fabric as a mesh anywhere in their slides. What they say that they keep same layout as Zen3/4 but improved latency. And technical details come from whistleblowers months before Zen5 release that they added ladders to their ring fabric - and did it by core pairing - actual fabric is 100% same as before but thanks to core pairing core can send data always on destination side removing need for packed traveling to other side of ring through it's ends, basically halving effective ring length which is pretty much in line what AMD states as their L3 latency improvement 3.5 cycles at 8 cpu ring.
We have die shot. Do research yourself and see how ring-based cpu dies always grow up in one dimension when adding ring stops and good luck finding any mesh-based die growing similarly only on one dimension. And then look that Ze5c die......
Discussing AMD’s Zen 5 at Hot Chips 2024
Hot Chips isn’t just a conference where companies give in-depth presentations on the architectures behind high performance chips.chipsandcheese.com
Ok, good. so you agree that tuning for max frequency makes the design use more power.Overdrive nodes very very very explicitly trade leakage characteristics for going zoom zoom.
Come on.
Forksheet is incremental and BSPDN will usually be thermally limited before hitting the clock wall.I dunno about that.
Nanosheet may not be a great win over finFET, but forksheet gains on top of that will be fairly decent.
And lest we forget, backside power delivery gains are also significant and imminent on the heels of nanosheet at TSMC.
Forksheet + BSPD should provide a pretty chunky overall gain to tide us over to CFET.
It just leaks more.so you agree that tuning for max frequency makes the design use more power.
They're limited by like a billion different things.Would you agree that DC processors are highly power/thermal limited?
Wow. So leaking more DOESN'T make it consume more power?It just leaks more.
They're limited by like a billion different things.