Question Zen 6 Speculation Thread

[adroc_thurston]

So leaking more DOESN'T make it consume more power?

Active power is helluva lot more things than that.

If so, then what IS the biggest one?

Bandwidth.
SP7 ain't a 16ch socket for kicks. It really needs all that and then some.

 

[Hulk]

AFAIK the max frequency of a process can be increased by increasing gate pitch, which moves the transistors farther apart, which in turn creates a lower current density. This allows for higher leakage transistors, which allows for higher max frequency and power. Nothing is free so you need more die area and idle power is higher as well as the increased power for the "new" max frequency. I read this in Anandtech a long time ago.

 

[Kronos1996]

Yup that’s always been the trade-off between speed and efficiency. In very basic terms, the closer transisters are together, the shorter wires can be. The less distance power has to travel, the less you lose to things like voltage drop-off. That’s why denser transistors = better power efficiency. But if you want speed, you have to spread them back out some which costs power.

 

[OneEng2]

AFAIK the max frequency of a process can be increased by increasing gate pitch, which moves the transistors farther apart, which in turn creates a lower current density. This allows for higher leakage transistors, which allows for higher max frequency and power. Nothing is free so you need more die area and idle power is higher as well as the increased power for the "new" max frequency. I read this in Anandtech a long time ago.

Yup that’s always been the trade-off between speed and efficiency. In very basic terms, the closer transisters are together, the shorter wires can be. The less distance power has to travel, the less you lose to things like voltage drop-off. That’s why denser transistors = better power efficiency. But if you want speed, you have to spread them back out some which costs power.

Exactly to both of you.

Active power is helluva lot more things than that.

Bandwidth.
SP7 ain't a 16ch socket for kicks. It really needs all that and then some.

I think I am done playing with the slippery watermelon seed on the wet table top. When you decide to have a serious conversation about the trade offs between design considerations vs moving the goal posts around in order to justify an incorrect assertion (ie clock speed is all that matters argument), let me know.

 

[reaperrr3]

Ok, good. so you agree that tuning for max frequency makes the design use more power.

I think you and adroc are somewhat talking past each other here:

The 12C CCD for desktop will seemingly be made on N2X, to ensure desktop clocks to 6+ GHz.
N2X roughly doubles leakage for ~5% higher transistor perf and higher supported voltages.

The 32C CCD for the many-core DC products will likely be made on either vanilla N2 or N2P.

There are rumors that there will be a variant of the 12C CCD made on N2P (less leakage, more power-efficient) for Mobile, so it's possible that DC SKUs based on 12C CCDs also use the N2P variant, although that's purely speculation on my end.
Maybe there won't even be any DC SKUs using the 12C CCDs, who knows.

But even if there were indeed DC SKUs using the 12C@N2X CCDs, we'd likely be talking about at most 144 cores vs. 256 on the big 32C-CCD-based SKUs, so there'll be more headroom in terms of thermals and power per core anyway.
At the end of the day, it depends on what their bigger customers want.
If some important customer wants an SKU with fewer cores but those clocked to the moon no matter the power consumption, they'll probably use those 12C-N2X-CCDs for that.

Would you agree that DC processors are highly power/thermal limited?

I'm no expert, but it's pretty obvious to me that at least for multi-threaded workloads, they're not.

They're rather area-limited for example, because power/thermals can be kept in check by going wider (more cores, lower clocks/voltages), but only if the process density improvements allow for it, so I'd say that's a bigger bottleneck, especially when it comes to SRAM/cache.
Physical limitations with all those memory channels and PCIe lanes coming off the IOD are probably increasingly becoming a problem, too.

 

[yuri69]

Btw this thread has already reached 100 pages and the launch of Zen 6 is still more than a year away.

 

[marees]

Btw this thread has already reached 100 pages and the launch of Zen 6 is still more than a year away.

Do we know how many different ccd configuration are in play at this moment ?

Do desktop & mobile ahare ccds or are they different?

 

[OneEng2]

I'm no expert, but it's pretty obvious to me that at least for multi-threaded workloads, they're not.

They're rather area-limited for example, because power/thermals can be kept in check by going wider (more cores, lower clocks/voltages), but only if the process density improvements allow for it, so I'd say that's a bigger bottleneck, especially when it comes to SRAM/cache.
Physical limitations with all those memory channels and PCIe lanes coming off the IOD are probably increasingly becoming a problem, too.

Since Turin high core count variants seem to clock around the 3-4Ghz range, it appears that the assumption that "only transistor clock speed matters" is incorrect. My thought is that these parts are EITHER power limited by the socket, or thermally limited. Regardless of which it is, it ISN'T clock speed limited.

Since the design is not clock speed limited, then it would follow that creating Zen 6 with only a high clock speed design considerations at the transistor level would not work well at all in high core count situations.

I don't believe that I am talking past anyone. It feels much more like someone is being intentionally oblique in their argument.

In most engineering discussions, using an absolute indicates a lack of understanding in the details of the design decision making process.

 

[OneEng2]

Do we know how many different ccd configuration are in play at this moment ?

Do desktop & mobile ahare ccds or are they different?

Not that I am aware of, but these are fantastic areas for discussion.

It seems very likely that the DC CCD's will be different than the desktop and laptop CCD's.

For HPC (Thread Ripper) I suspect it can share the DC CCD's.

Within desktop and laptop, we know there will be a 12c CCD, but we don't know if there will be lesser core CCD's. In theory, AMD could use the same 12c CCD and bin them into CCD's that pass with:

1. 2 functioning cores
2. 4 functioning cores
3. 6 functioning cores
4. 8 functioning cores
5. 10 functioning cores
6. 12 functioning cores

Now if you include a 2nd CCD within a processor you get a silly number of possibilities.

Since there is little room in the market for so much variation, I suspect it will be artificially limited to a fixed set of marketing numbers.

 

[marees]

Within desktop and laptop, we know there will be a 12c CCD, but we don't know if there will be lesser core CCD's. In theory, AMD could use the same 12c CCD and bin them into CCD's that pass with:

1. 2 functioning cores
2. 4 functioning cores
3. 6 functioning cores
4. 8 functioning cores
5. 10 functioning cores
6. 12 functioning cores

Now if you include a 2nd CCD within a processor you get a silly number of possibilities.

Since there is little room in the market for so much variation, I suspect it will be artificially limited to a fixed set of marketing numbers.

I get the feeling that desktop will have a single ccx 12p ccd whereas mobile would have a dual ccx 4p 8c ccds

& then we await the lp cores also

So many permutations & combinations

 

[jpiniero]

I was wondering if AMD might just copy Intel and go with Big+Little dies for all desktop/mobile.

I think the main question is will they still be able to do vcache if it's not sharing the Server die.

 

[GTracing]

Not that I am aware of, but these are fantastic areas for discussion.

It seems very likely that the DC CCD's will be different than the desktop and laptop CCD's.

For HPC (Thread Ripper) I suspect it can share the DC CCD's.

Within desktop and laptop, we know there will be a 12c CCD, but we don't know if there will be lesser core CCD's. In theory, AMD could use the same 12c CCD and bin them into CCD's that pass with:

1. 2 functioning cores
2. 4 functioning cores
3. 6 functioning cores
4. 8 functioning cores
5. 10 functioning cores
6. 12 functioning cores

Now if you include a 2nd CCD within a processor you get a silly number of possibilities.

Since there is little room in the market for so much variation, I suspect it will be artificially limited to a fixed set of marketing numbers.

imo, a different CCD with less cores doesn't make sense. A 6 core CCD would reduce area by less than half, and you still have the full IO die and the same packaging. If the 12 core SKU costs $100 and the 6 core costs $75, I don't think it's worth it. 6 core desktop CPUs are going to be budget and niche in 2026. Zen5 can be repurposed for the bottom end of the stack.

Here's how I imagine the lineup will look.

• desktop io die that uses regular DDR
  • 24 core and 20 core R9
  • 12 core R7
  • 8 or 10 core R5
• premium mobile io die that's basically the sucessor to Strix Point. One CCD link. LPDDR support, bigger iGPU, an SLC, and maybe LP cores.
  • 12 core R9
  • 10 core R7
• mainstream/budget monolithic chip with 8 cores (6 of which are dense). LPDDR support, moderate sized iGPU
  • 8 core R5

All chiplet consumer parts would use the same CCD.

 

[Joe NYC]

imo, a different CCD with less cores doesn't make sense. A 6 core CCD would reduce area by less than half, and you still have the full IO die and the same packaging. If the 12 core SKU costs $100 and the 6 core costs $75, I don't think it's worth it. 6 core desktop CPUs are going to be budget and niche in 2026. Zen5 can be repurposed for the bottom end of the stack.

Here's how I imagine the lineup will look.

• desktop io die that uses regular DDR
  • 24 core and 20 core R9
  • 12 core R7
  • 8 or 10 core R5
• premium mobile io die that's basically the sucessor to Strix Point. One CCD link. LPDDR support, bigger iGPU, an SLC, and maybe LP cores.
  • 12 core R9
  • 10 core R7
• mainstream/budget monolithic chip with 8 cores (6 of which are dense). LPDDR support, moderate sized iGPU
  • 8 core R5

All chiplet consumer parts would use the same CCD.

Those configurations make sense.

As far as Medusa Halo, it could have 2 CCDs for 24 cores, but if there is a Medusa Halo with a bigger iGPU, single CCD version with the big iGPU would be enough for majority of users.

In majority of client CPU workloads, 12 core Medusa Halo will likely be faster than 16 core Strix Halo.

 

[StefanR5R]

Since Turin high core count variants seem to clock around the 3-4Ghz range, it appears that the assumption that "only transistor clock speed matters" is incorrect. My thought is that these parts are EITHER power limited by the socket, or thermally limited. Regardless of which it is, it ISN'T clock speed limited.

Their maximum boost clock speed seems to be a switching speed limit. Cf. Zen 5 speculation thread for why it's not 5.7 GHz like with Ryzens but 5.0 GHz or less. However, in well threaded loads, they operate of course at way less than max_f, and that's because of power usage. T_junction,max seems to be configured to 100 °C (I briefly searched and found only a 3rd party source for this) which does not look like a relevant limit to me if cooler/chassis/environment are properly done.

Edit: As for Zen 6/ Venice, my expectation is that they will keep it similar as with Zen 5/ Turin, the latter having either a 5.0 GHz 8c CCD or a denser 3.7 GHz 16c CCD. The only question to me is if there will be just 2 or even 3 CCD types for Venice — not just because of different clock speed vs. density targets but perhaps also because of packaging variants. Edit 2, I also expect that Venice won't regress vs. Turin WRT max_f; they might rather bump it up further in at least the per-core performance optimized SKUs.

 

[OneEng2]

Their maximum boost clock speed seems to be a switching speed limit. Cf. Zen 5 speculation thread for why it's not 5.7 GHz like with Ryzens but 5.0 GHz or less. However, in well threaded loads, they operate of course at way less than max_f, and that's because of power usage. T_junction,max seems to be configured to 100 °C (I briefly searched and found only a 3rd party source for this) which does not look like a relevant limit to me if cooler/chassis/environment are properly done.

Edit: As for Zen 6/ Venice, my expectation is that they will keep it similar as with Zen 5/ Turin, the latter having either a 5.0 GHz 8c CCD or a denser 3.7 GHz 16c CCD. The only question to me is if there will be just 2 or even 3 CCD types for Venice — not just because of different clock speed vs. density targets but perhaps also because of packaging variants. Edit 2, I also expect that Venice won't regress vs. Turin WRT max_f; they might rather bump it up further in at least the per-core performance optimized SKUs.

Agree.

So you are saying that you don't think the 3.7Ghz on the 16c CCD is thermally limited, but rather socket power limited?

 

[ShimmerBlade]

I don't see N2X on TSMC roadmap for 2026.
Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/355121-tsmc-2025-technical-symposium-briefing/

 

[Hulk]

Btw this thread has already reached 100 pages and the launch of Zen 6 is still more than a year away.

Seeing how these threads grow exponentionally as we approach the release date and then die suddenly after launch I have a feeling it's going grow a lot over the next year!

 

[CouncilorIrissa]

Btw this thread has already reached 100 pages and the launch of Zen 6 is still more than a year away.

Still got nothing on the previous one. I find it 32% more boring.

 

[Hulk]

Still got nothing on the previous one. I find it 32% more boring.

Congrats. Very efficient way to diss every poster in this thread in only 12 words and 1 number.

 

[fastandfurious6]

I think most stuff has already been discussed and it's going to mostly be offtopic/peripheral stuff or wacky theories up until new radical leaks come out next year

 

[RTX]

Wow. So leaking more DOESN'T make it consume more power?

TSMC's 3nm update: N3P in production, N3X on track

The last and final FinFET node from TSMC lives on.

www.tomshardware.com

N3P uses more power in that chart when both are the same speed though.

 

[branch_suggestion]

Still TSMC A-next will probably be a clean sheet forksheet node and not N3+++ like A16.

And that didn't last long, A14 is just a new GAA node.
Boring, no SPR in the first version either so they are playing it very safe.
Don't see much reason to use it early over matured A16 unless the wafer cost is good.

 

[msj10]

I don't see N2X on TSMC roadmap for 2026.
Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/355121-tsmc-2025-technical-symposium-briefing/

yeah AMD have to settle for N2P if they want to launch in 2026

 

[StefanR5R]

So you are saying that you don't think the 3.7Ghz on the 16c CCD is thermally limited, but rather socket power limited?

I think neither one.
f_base is 2.25 GHz (9965: 192c@500W)/ 2.4 GHz (9745: 128c@400W). Actual real-world all-threads loads will certainly be power-limited at clocks anywhere between f_base and f_max. (I don't have a Turin-dense myself, nor do I recall right away if anybody has published actual Turin-dense clock speeds in benchmarks or in practice yet.)

 

[eek2121]

I don't see N2X on TSMC roadmap for 2026.
Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/355121-tsmc-2025-technical-symposium-briefing/

That is just a poorly designed image. I wouldn’t read too much into it. I also wouldn’t assume Zen 6 is launching next year without official confirmation.