Question Zen 6 Speculation Thread

[LightningZ71]

Things we do know for certain:
AMD has been producing a separate die for DC from desktop for a while if you consider the C core high core count dies as separate since they don't appear in consumer products. AMD's die for Strix Halo appears different than their desktop die from recent die shots. That's at least three different CCDs for Zen5 so far. This leads us to believe that there will be additional segmentation going forward.

L3 cache scaling slowed drastically from N5 to N3. The most notable density increase came from a cell rearrangement. BSPD will allow another density increase, but that's not until A16.

Wafer costs are still increasing each generation and now at a faster rate than density is. This means that leading edge products will have to be viciously efficient, putting pressure on non-scaling parts to get evicted from the CCD.

Die stacking is getting more experience in the industry and techniques and processes are improving. It's going to become more common.

My prediction is that the trend will start where cache levels that can tolerate higher latencies will get evicted in order. L3 is already moving as seen by X3D products. It will get more thorough in the future to where, eventually, no core but the most compact and low end will have it on the CCD.

TSMC and AMD are already experienced in making cache and cost optimized chiplets. With the introduction of N3C, this continues. I expect that there will be an A16C since BSPD will bring a cache density boost. I realize that the C isn't specifically about cache, but cost optimized nodes will be the foundation for it.

At some point soon, AMD will have to produce a CCD with no L3, just buffers, control logic and VIAs to a stacked L3 cache chiplets. It'll probably have changes to the L2 and what passes as L1 caches to hide the extra few cycles of latency that will cost.

Intel is in much the same boat and will be chasing similar paths themselves.

 

[511]

BSPDN doesn't bring SRAM Boost if anything it reduces density

 

[Josh128]

The new 12 core CCD, assuming it has the same L3 per core and 12 core CCX, should make for, by far, the most potent X3D chips to date. The CCD will come standard with 48MB of on die L3 and assuming AMD again stick to 64MB V-cache, give a total of 112MB of L3, unified across 12 cores! That, plus 10% IPC gains and potentially some memory speed and latency improvements, PLUS likely another 200-300 MHz clock speed increase, should make Zen 6 X3D a stupendous gaming chip.

If they happen to also increase the L3 on the v-cache die, it will be even more ridiculous. Seems like the stars are aligning for Zen 6 to be quite impressive. Intel has their work cut out for them even if 18A is all they claim it will be.

 

[StefanR5R]

AT has no idea what Zen 7 is going to be.

Although #2,568 ventured off to Zen 7, I understood #2,569 as a followup to the discussion whether the Zen 6 32c CCD is simply going to be a Zen 5 16c CCD doubled and shrunk, or organized differently.

 

[Hitman928]

BSPDN doesn't bring SRAM Boost if anything it reduces density

Intel showed increased SRAM density with their BSPDN, you just have to not use it in the bit cell. TSMC’s BSPDN is more advanced and has a good chance of allowing bit cell density improvements as well.

 

[511]

Intel showed increased SRAM density with their BSPDN, you just have to not use it in the bit cell. TSMC’s BSPDN is more advanced and has a good chance of allowing bit cell density improvements as well.

We will have to see with implementation by TSMC but yeah it's an advanced method vs powerVia.

 

[511]

The new 12 core CCD, assuming it has the same L3 per core and 12 core CCX, should make for, by far, the most potent X3D chips to date. The CCD will come standard with 48MB of on die L3 and assuming AMD again stick to 64MB V-cache, give a total of 112MB of L3, unified across 12 cores! That, plus 10% IPC gains and potentially some memory speed and latency improvements, PLUS likely another 200-300 MHz clock speed increase, should make Zen 6 X3D a stupendous gaming chip.

If they happen to also increase the L3 on the v-cache die, it will be even more ridiculous. Seems like the stars are aligning for Zen 6 to be quite impressive. Intel has their work cut out for them even if 18A is all they claim it will be.

Cough cough 144MB L3 Cache variant from Intel

 

[jpiniero]

You want less NUCA domains, not more.

Good answer... but I guess that answers why there would be a server/client split. Because you'd have to think they would also increase the core count on the regular die too... and that'd start to get really expensive, esp if the regular server die is also on N2.

 

[reaperrr3]

The new 12 core CCD, assuming it has the same L3 per core and 12 core CCX, should make for, by far, the most potent X3D chips to date. The CCD will come standard with 48MB of on die L3 and assuming AMD again stick to 64MB V-cache, give a total of 112MB of L3, unified across 12 cores! (...)

If they happen to also increase the L3 on the v-cache die, it will be even more ridiculous.

I assume that due to how L3 and V-Cache are connected, the V-Cache will have to be 48MB*x as well.

Combining 48MB L3 with 64 MB V-Cache would likely only work if the V-Cache was an L4.
But since it's technically a capacity upgrade of the L3, aspects like associativity and bandwidth need to be the same, so when the CCD has 48MB L3, the V-Cache has to be either 48, 96, 144 or 192 MB (if that many layers are supported).

 

[511]

If the space is missing they have to use copper pillars to support uneven die size if the Cache stays to the bottom.

 

[Joe NYC]

SRAM bit cell scaling has been dead for few years only N3B had scaling but it was so bad they reverted it back.
The cost to put L3 on between N5 and N2 is a big increase so it makes sense to use HB with N4P as the base die with N2 but the question remains when are we going to see it.

Why N4 (or N4P) for Base as opposed to N6? Cost per bit and wafer availability should favor N6.

 

[adroc_thurston]

Why N4 (or N4P) for Base as opposed to N6? Cost per bit and wafer availability should favor N6.

Because you need to run SRAM macro at Real Actual Speeds.

 

[soresu]

BSPDN doesn't bring SRAM Boost if anything it reduces density

Why though?

I don't understand how shifting power delivery metal layers to the backside of the die would reduce density.

 

[OneEng2]

BSPDN doesn't bring SRAM Boost if anything it reduces density

That is possible. SRAM only accounts for 5-7W of power on 9950X3D while the 2 CCD's core processors munch through over 100W.

As a result, SRAM is less likely to shrink with BSPDN than the cores are. The cores may well shrink though as logic gates routing is much more complex .... and it draws way way more power.

 

[Hitman928]

Why though?

I don't understand how shifting power delivery metal layers to the backside of the die would reduce density.

With Intel’s method, you still need room for the contact in the horizontal so density goes down. You get an electrical benefit but Intel found it not to be worth the density impact. You can still use it in the SRAM array for the control logic and such, just not in the bitcells.

 

[soresu]

From what I am seeing it looks like Intel described this technology backside (the dirty kind) backwards, because I still can't see how moving it from one side of the die to another should affect density at all.

Perhaps their explaining it in the context of backside vs frontside illumination of image sensors wasn't the right analogue?

 

[Hitman928]

From what I am seeing it looks like Intel described this technology backside (the dirty kind) backwards, because I still can't see how moving it from one side of the die to another should affect density at all.

Perhaps their explaining it in the context of backside vs frontside illumination of image sensors wasn't the right analogue?

For density, moving the power routing to the backside helps because when you have front side power delivery, you have both power and logic being routed to basically the same place with roughly the same path to get there so there ends up being a lot of congestion and you have to spread things out so they don’t run into each other.

With backside power, the power delivery and logic follow completely different paths up until the very end (or for TSMC’s method they never come together) so that relieves a significant amount of the congestion and lets you improve density.

 

[soresu]

For density, moving the power routing to the backside helps because when you have front side power delivery, you have both power and logic being routed to basically the same place with roughly the same path to get there so there ends up being a lot of congestion and you have to spread things out so they don’t run into each other.

With backside power, the power delivery and logic follow completely different paths up until the very end (or for TSMC’s method they never come together) so that relieves a significant amount of the congestion and lets you improve density.

Ah thankyou, that makes a lot more sense.

Does it improve signal integrity at all for IO by moving the power further away?

 

[Hitman928]

Ah thankyou, that makes a lot more sense.

Does it improve signal integrity at all for IO by moving the power further away?

Maybe not as much for the IO itself (this typically refers to a specific block of the chip) but if you mean the logic signals, then yes. The main effect comes from the reduced parasitics and cleaner power delivery (as well as more efficient power delivery) which allows the transistors to more cleanly pass the signals through the chip.

 

[soresu]

Maybe not as much for the IO itself (this typically refers to a specific block of the chip) but if you mean the logic signals, then yes. The main effect comes from the reduced parasitics and cleaner power delivery (as well as more efficient power delivery) which allows the transistors to more cleanly pass the signals through the chip.

Nais, in the unlikely event that Vaire's reversible computing revolution ever happens in CPUs and GPUs that should reduce the remaining power losses some.

 

[Joe NYC]

Because you need to run SRAM macro at Real Actual Speeds.

If AMD were to completely remove L3 from the main die (and possibly increase L2), then the whole L3 can be reengineered to work at half speed in the V-Cache die, with minimum loss of latency.

L3 latency is already > 40 clock cycles, and going to V-Cache already adds (apparently) about 2 clock cycles, to half speed cache, with practically unlimited width should result in very tiny delays - 1 cycle. That's assuming AMD is already not doing it.

Running at half the clock speed could also allow lower voltage and with it, lower power consumption.

 

[adroc_thurston]

then the whole L3 can be reengineered to work at half speed in the V-Cache die, with minimum loss of latency

Uh no brother that's not how that works.

L3 latency is already > 40 clock cycles, and going to V-Cache already adds (apparently) about 2 clock cycles, to half speed cache, with practically unlimited width should result in very tiny delays - 1 cycle. That's assuming AMD is already not doing it.

It adds 4 cycles and half speed caches are just not happening, that's terribly slow under all circumstances.

Running at half the clock speed could also allow lower voltage and with it, lower power consumption.

Active cache power just isn't all that high.

 

[fastandfurious6]

by the time zen 7 is supposed to come out the computing landscape's variables may have radically changed

 

[LightningZ71]

Zen7 is already deep in design and starting to look at production methods if the past is any indicator.

 

[511]

The production option is either A16/A14. A16 is N2+BSPDN or A14