Question Zen 6 Speculation Thread

[Kepler_L2]

The production option is either A16/A14. A16 is N2+BSPDN or A14

A14 is too late for Zen7, A16 is most likely since it's a half node from N2.

 

[511]

A14 is too late for Zen7, A16 is most likely since it's a half node from N2.

Makes sense TSMC has switched to 3 year cadence now
N5 2020 Produced
N3 2023 Products
N2 2026 products
A14 2029 products?

 

[Joe NYC]

Here is a dumb question about the "backside power delivery"
- what is the back side?
- why not call it motherboard side and heatsink side?
- why not call it silicon transistor side vs. wire side (before BSPD)
- what happens to this terminology in a flip chip? They say the "Up" and "Down" are flipped, without ever explaining what is "Up" and what is "Down"

Here comes the real question:
- if the "backside power delivery" means power on the side away from the motherboard, how does this power get there? It would make sense for the power to be on the motherboard side, but then, I am guessing, multiple layers of metal connections, if on heatsink side, would present some thermal resistance...

Edit: the context to it is how this can work with V-Cache

 

[Hitman928]

Here is a dumb question about the "backside power delivery"
- what is the back side?
- why not call it motherboard side and heatsink side?
- why not call it silicon transistor side vs. wire side (before BSPD)
- what happens to this terminology in a flip chip? They say the "Up" and "Down" are flipped, without ever explaining what is "Up" and what is "Down"

Here comes the real question:
- if the "backside power delivery" means power on the side away from the motherboard, how does this power get there? It would make sense for the power to be on the motherboard side, but then, I am guessing, multiple layers of metal connections, if on heatsink side, would present some thermal resistance...

Edit: the context to it is how this can work with V-Cache

- what is the back side?

Backside is the side opposite the metal layers when looking at a vertical cross-section. Front side has the metal layers and is traditionally where the pads are.

- why not call it motherboard side and heatsink side?

Because you can have flip chip and non flip chip designs, so this wouldn’t help you know what’s what in the die.

- why not call it silicon transistor side vs. wire side (before BSPD)

Too cumbersome.

- what happens to this terminology in a flip chip? They say the "Up" and "Down" are flipped, without ever explaining what is "Up" and what is "Down"

Nothing happens. Backside is still backside, it’s just now flip chip orientation so the backside is now the “top” for the purpose of this discussion.

- if the "backside power delivery" means power on the side away from the motherboard, how does this power get there?

You either use TSVs to go through the logic die to the BSPDN die and then back to the backside of the logic die, or the logic die is no longer flip chip and sits “on top” of the BSPDN die.

-Edit: the context to it is how this can work with V-Cache

Not sure if AMD is really planning to use BSPDN in the near future, but maybe the V-cache die and BSPDN die are one die in this scenario. Or you get into cache filled interposers or something. Not sure, haven’t really thought about it.

 

[511]

Here is a dumb question about the "backside power delivery"
- what is the back side?
- why not call it motherboard side and heatsink side?
- why not call it silicon transistor side vs. wire side (before BSPD)
- what happens to this terminology in a flip chip? They say the "Up" and "Down" are flipped, without ever explaining what is "Up" and what is "Down"

Here comes the real question:
- if the "backside power delivery" means power on the side away from the motherboard, how does this power get there? It would make sense for the power to be on the motherboard side, but then, I am guessing, multiple layers of metal connections, if on heatsink side, would present some thermal resistance...

Edit: the context to it is how this can work with V-Cache

This video explains it nicely

 

[Mopetar]

That s still too high, AMD never used the other processes at this point of the curves, rather when it reach +2Q, wich amount to one year from now plus the necessary time to have enough inventory, so a total of roughly 6 quarters, wich lead us to early Q4 2026 at best.

There's no reason they couldn't. Their chiplets are smaller than Apple's A-series SoCs and AMD sells a lot of six core CPUs so even if the defect density is still high they're not all that bad off since the likelihood of dead silicon is fairly low.

TSMC has to sell the capacity to someone and they can negotiate special pricing until defect density hits some predefined target if a company like AMD would otherwise be hesitant to buy in.

I assume that due to how L3 and V-Cache are connected, the V-Cache will have to be 48MB*x as well.

No it wouldn’t. The additional v-cache just increases the associativity of the cache, so it doesn't need to match the size at all and only needs to be a multiple of the size of a set.

While there's theoretically nothing stopping them from designing a cache that functions differently, it would require a lot of added complexity as the cache needs to be able to decode for multiple modes. There's also not a lot of benefit to making an L3 with larger blocks/lines than the L2 and L1 cache support. It does turn one (or maybe two) misses on highly sequential data access into hits, but the added latency to fill and access larger cache lines may not be worth the trade off as a lot of software is already optimized around L1/L2 cache sizes.

Maybe if AVX became a lot more popular it would be worth doing something like that so you can load a massive vector into L3 cache, but existing code bases wouldn't benefit all that much. Servers likely would just want more sets anyway so they don't benefit from the design change either.

 

[inquiss]

They can announce it during launch to be available in X months, how about that? And start pre-orders immediately. Then people have certainty.

Also Apple prepares tens of millions of iPhones for launch - somehow they can do it, and it's far more effort than put 1000 chips into trays and off you go.

On your first point, they could do. People already expect it so I doubt it Osbornes that much. Depends if other products are using the packaging though, if server products use that more next gen then they might not know when they'll release the desktop version because you'd want to sell as much as possible in server, if packaging is the bottleneck.

On the second point. Apple don't by having lots of capacity and stocking for launch. If they have 3D stacked cache on their chips they'd be limited in production volumes and, even if that were not the case, would have to launch later than they do. That simple really.

 

[basix]

I assume that due to how L3 and V-Cache are connected, the V-Cache will have to be 48MB*x as well.

I don't know if required but at least we hope for that 144MByte L3$ sounds great.

When I look at the Zen 5 CCD and assuming that the 12C Die gets a little bit smaller (e.g. 60mm2 instead of 70mm2, best case), it would be a nice fit to use N4C for the 96 MByte cache chiplet. Memory density should fit really well.
So we have a roughly ~1.2x smaller Die at a ~1.25x more expensive node (according to early AMD estimates of N7 and N5) or in other words roughly the same cost for the cache Die. Not too bad for 1.5x memory capacity.
The N2 CCD is probably a bit more expensive despite the smaller Die area.

But even if it should stay at ~70mm2 it is probably worthwile to go for 96MByte instead of only 64MByte. The cost difference overall ist not that huge (N2 CCD + X3D Cache-Die + IOD). And the additional area could get used for some deep trench capacitors to boost CPU clock rates (see Graphcore IPU, 2nd Link). And we keep the 12MByte/Core L3$ ratio from all prior V-Cache CPUs (SW tuning/compatibility).

Spoiler: Zen 5 X3D

 

[Makaveli]

I don't know if required but at least we hope for that 144MByte L3$ sounds great.

When I look at the Zen 5 CCD and assuming that the 12C Die gets a little bit smaller (e.g. 60mm2 instead of 70mm2, best case), it would be a nice fit to use N4C for the 96 MByte cache chiplet. Memory density should fit really well.
So we have a roughly ~1.2x smaller Die at a ~1.25x more expensive node (according to early AMD estimates of N7 and N5) or in other words roughly the same cost for the cache Die. Not too bad for 1.5x memory capacity.
The N2 CCD is probably a bit more expensive despite the smaller Die area.

But even if it should stay at ~70mm2 it is probably worthwile to go for 96MByte instead of only 64MByte. The cost difference overall ist not that huge (N2 CCD + X3D Cache-Die + IOD). And the additional area could get used for some deep trench capacitors to boost CPU clock rates (see Graphcore IPU, 2nd Link). And we keep the 12MByte/Core L3$ ratio from all prior V-Cache CPUs (SW tuning/compatibility).

Spoiler: Zen 5 X3D

I can see this with the smaller cores and more room to move the cache up from 64 to 96.

 

[Doug S]

On the second point. Apple don't by having lots of capacity and stocking for launch. If they have 3D stacked cache on their chips they'd be limited in production volumes and, even if that were not the case, would have to launch later than they do. That simple really.

That's not really a problem for Apple. They aren't likely to stack cache on iPhone SoCs, or base level Apple Silicon. It would probably be something they did only for Max dies, and not all of them. Those are lower volume parts and the products containing them aren't released on a set schedule so the production volume limitations and having to launch a bit later wouldn't be an issue.

 

[Jan Olšan]

A14 is too late for Zen7, A16 is most likely since it's a half node from N2.

Is it? It feels more like a parallel technology. It is coming later than N2, but parallel to N2P and it's apparently a backside-power-delivery enabled version of N2P.

Apparently TSMC is branching between processes with backside power delivery and processes without.
N2P -> A14 is the non-BPD line and A16 -> (yet unnanounced process that will be A14+BPD) is the second one with BPD.

Actually I wonder what will AMD use, will they go for backside power delivery? If yes, then that rules A14 out. Well, of course they can use both for different products.

(BTW, the recent TSMC slides also put N2X production only into 2027, so potentially that contradicts MLID info about Zen 6 using N2X, I'd expect it to be on plain N2 instead. Actually that kind of goes without saying - if AMD was one of the first clients taping out a chip - for Genoa - then that chip can't be using N2X).

 

[inquiss]

That's not really a problem for Apple. They aren't likely to stack cache on iPhone SoCs, or base level Apple Silicon. It would probably be something they did only for Max dies, and not all of them. Those are lower volume parts and the products containing them aren't released on a set schedule so the production volume limitations and having to launch a bit later wouldn't be an issue.

So I think what you're saying is, yes, if Apple added 3D vcache to a part it would launch later. So I think you're agreeing that if AMD launched vcache first it would just be a delay of everything else. Fairly sure you're agreeing with me, otherwise I'm missing the point of your post. If I am by all means let me know what I've missed.

 

[RTX]

- if the "backside power delivery" means power on the side away from the motherboard, how does this power get there?

You either use TSVs to go through the logic die to the BSPDN die and then back to the backside of the logic die, or the logic die is no longer flip chip and sits “on top” of the BSPDN die.

-Edit: the context to it is how this can work with V-Cache

Not sure if AMD is really planning to use BSPDN in the near future, but maybe the V-cache die and BSPDN die are one die in this scenario. Or you get into cache filled interposers or something. Not sure, haven’t really thought about it.

There's also Vertical Power Delivery ( separate from backside power ) moves the pmics under the cpu/gpu dies.

 

[Win2012R2]

If they have 3D stacked cache on their chips they'd be limited in production volumes and, even if that were not the case, would have to launch later than they do. That simple really.

No: if Apple had 3D stacked cache on their chips then they would make sure they got enough capacity to sell sell sell. That's what Apple would do.

What's harder, slower and more expensive to make - N2 fab or create enough capacity for 3D cache integration?

 

[511]

Packing is easier to setup than N2 Fab

 

[OneEng2]

Is it? It feels more like a parallel technology. It is coming later than N2, but parallel to N2P and it's apparently a backside-power-delivery enabled version of N2P.

Apparently TSMC is branching between processes with backside power delivery and processes without.
N2P -> A14 is the non-BPD line and A16 -> (yet unnanounced process that will be A14+BPD) is the second one with BPD.

Actually I wonder what will AMD use, will they go for backside power delivery? If yes, then that rules A14 out. Well, of course they can use both for different products.

(BTW, the recent TSMC slides also put N2X production only into 2027, so potentially that contradicts MLID info about Zen 6 using N2X, I'd expect it to be on plain N2 instead. Actually that kind of goes without saying - if AMD was one of the first clients taping out a chip - for Genoa - then that chip can't be using N2X).

From what I have been able to read and discuss, BSPDN isn't a slam dunk for everything; however, it works especially well for some things.

I like that TSMC intends to make their libraries compatible between N2 and A16 w/ BSPDN. This will make it easy for design houses to test their designs on either process to determine which process works best for their design. To date, Intel does not have anything like this that I am aware of.

 

[511]

You have to redo your flow for BSPDN though

 

[branch_suggestion]

Not sure if AMD is really planning to use BSPDN in the near future, but maybe the V-cache die and BSPDN die are one die in this scenario. Or you get into cache filled interposers or something. Not sure, haven’t really thought about it.

Actually I wonder what will AMD use, will they go for backside power delivery?

WIPO - Search International and National Patent Collections

It might be part of their plans.

 

[511]

WIPO - Search International and National Patent Collections

It might be part of their plans.

We saw Admantine patent as well with Intel and we know how that turned out.

 

[adroc_thurston]

We saw Admantine patent as well with Intel and we know how that turned out.

AMD isn't Intel in case you forgot that.

 

[511]

AMD isn't Intel in case you forgot that.

Precisely but patents don't tell the whole picture.

 

[Jan Olšan]

AMD isn't Intel in case you forgot that.

Z-RAM multi-layer 3D V-Cache on FD-SOI any time now! Serionxly

 

[inquiss]

No: if Apple had 3D stacked cache on their chips then they would make sure they got enough capacity to sell sell sell. That's what Apple would do.

What's harder, slower and more expensive to make - N2 fab or create enough capacity for 3D cache integration?

I don't think you understand some basics here. Adding 3D vcache takes time. From wafer start to product takes longer. You can make a chip without vcache in x time or you can make a chip worth 3D vcache in x+y time. Y is non zero. Capacity or not capacity they would have to launch later.

 

[Thibsie]

The problem is the SoIC capacity for AMD

 

[Win2012R2]

Capacity or not capacity they would have to launch later.

No, it does NOT have to launch later - they can first accumulate non-3D chips to actually have stock for launch, and some 3D ones that will be super popular and out of stock quickly, we are talking months here max, not years, so it's totally doable and should have been done.

The problem is the SoIC capacity for AMD

Is the problem with SoIC that it is God level tech that can not be replicated because all knowledge how it was done is now totally lost?

If AMD makes commitment, and it can't be too expensive, this ain't N2 fabs, then everything will be done with bells on. That's the problem - AMD.