Question Zen 6 Speculation Thread

[OneEng2]

Venice is N2 AMD made a PR with it for Desktop I t

Do you have a link? I thought the announcement was only Venice?

288C/T

How do you figure the CCD's will be laid out in that? All e core? If it's e core then it will have no SMT and only be able to operate AVX 256bit pathways correct?

DMR is 18AP

I wonder though. BSPDN may have issues with hot spots limiting clock speeds. This may not be an issue on DC chips. DMR will be all P cores with SMT? For a design that was supposed to be released in late 2025, there has been very little leaked on it. Seeing how we are closing in on the end of this half of 2025, I am starting to smell a delay here .

 

[511]

Do you have a link? I thought the announcement was only Venice?

Yeah it was Venice looks like I got confused usually and reuses Desktop and Server CCD

How do you figure the CCD's will be laid out in that? All e core? If it's e core then it will have no SMT and only be able to operate AVX 256bit pathways correct?

24 Core Tile 12 of those 24*12=288 Cores if what adroc syays is true than it will be 24*8=192 Cores

I wonder though. BSPDN may have issues with hot spots limiting clock speeds. This may not be an issue on DC chips. DMR will be all P cores with SMT? For a design that was supposed to be released in late 2025, there has been very little leaked on it. Seeing how we are closing in on the end of this half of 2025, I am starting to smell a delay here .

DMR was never 2025 ? And Clearwater Forest is already delayed to Q1 26

 

[Tarkin77]

Well they have no customers for any of the server Atoms.
RRF is entirely dead too.

whats RRF??

 

[511]

whats RRF??

Rouge River Forest a Atom based Server CPU Supposed to be based on Arctic Wolf and with AVX-10.2/APX it would be good vs Zen6 but it's canned in favor of another variant of DMR.

 

[adroc_thurston]

Who told you that ?

Came to me in a dream.

This is true from what I heard recently they are making a bigger P core variant instead of RRF.

More like "no one wants Atoms".

 

[511]

Came to me in a dream.

Nice Dream 🤣

More like "no one wants Atoms".

People don't understand the value in atom these are not weak cores this is a better core in integer performance than Zen4/RWC and vector performance as well not counting AVX-512 ofc

 

[adroc_thurston]

People don't understand the value in atom

Well there ain't any.

these are not weak cores this is a better core in integer performance than Zen4/RWC

Kind of.
They're really really not efficient while getting anywhere there (Tremont was the last truly efficient Atom).

and vector performance as well not counting AVX-512 ofc

Oh no Atom SIMD still sucks ass.

 

[511]

Well there ain't any.

Kind of.
They're really really not efficient while getting anywhere there (Tremont was the last truly efficient Atom).

Oh no Atom SIMD still sucks ass.

OFC that is why Intel is going Unified core with atom as a base? and what things are you basing this on if anything Atom cores with very good PPA this is just market failing to understand it's value. Let's see in 2 years when atom will have full ISA including APX/AVX 10.2.

This is a Zen 6 thread so i am going off topic here do we have a P ve E core thread anyone?

 

[adroc_thurston]

OFC that is why Intel is going Unified core with atom as a base?

Because what else could they do? IDC sucks and Royal Core went tits up.

and what things are you basing this on if anything Atom cores with very good PPA this is just market failing to understand it's value

They're good on area and not the other two factors.
That ARL-H 8c/8t versus STX1 8c/8t SIR run was scathing.

Let's see in 2 years when atom will have full ISA including APX/AVX 10.2.

See the ISA is not the only gating here. Good SIMD setup has little to no glass jaws, which gets kinda really damn expensive on area.

 

[511]

Because what else could they do? IDC sucks and Royal Core went tits up.

Royal was horrendous if only you knew about Royal man it was such a mess of a arch in terms of PPA.

They're good on area and not the other two factors.
That ARL-H 8c/8t versus STX1 8c/8t SIR run was scathing.

The PnP characteristics are good as well ARL-H is a borked implementation holding back both the P and E cores.

See the ISA is not the only gating here. Good SIMD setup has little to no glass jaws, which gets kinda really damn expensive on area.

Gracemont was laughable in SIMD perf Skymont was very big Arctic wolf is going to big as well .

 

[adroc_thurston]

Royal was horrendous

Yeah I know.

The PnP characteristics are good as well ARL-H is a borked implementation holding back both the P and E cores.

They ain't and ARL-H has not much wrong about it.

Gracemont was laughable in SIMD perf Skymont was very big Arctic wolf is going to big as well .

They have a billion glass jaws as a result of extra tight area budgets.
Atoms won't have a real SIMD unit until unified core and you know it.

 

[marees]

Well there ain't any.

Kind of.
They're really really not efficient while getting anywhere there (Tremont was the last truly efficient Atom).

Oh no Atom SIMD still sucks ass.

How much of this is an ISA/Arch problem vs fab issue ?

Can Intel just switch everything to TSMC ??

 

[adroc_thurston]

How much of this is an ISA/Arch problem vs fab issue ?

It's all down to their microarch. GRT and SKT have great perf density area-wise at the expense of power.
ARL-H is on N3b and uhhhh.

Can Intel just switch everything to TSMC ??

They're too broke and their market position too precarious for that.

 

[511]

They ain't and ARL-H has not much wrong about it.

poor L3 fabric which affects performance conservative D2D/NGU clocks?

They have a billion glass jaws as a result of extra tight area budgets.
Atoms won't have a real SIMD unit until unified core and you know it.

that's too far away Arctic Wolf will have it and i am pretty sure of it

 

[adroc_thurston]

poor L3 fabric which affects performance conservative D2D/NGU clocks?

It has 3 times the accessible L3 of the STX1 dense cluster at similar clocks.

that's too far away Arctic Wolf will have it and i am pretty sure of it

Atom guys are not building a real SIMD unit until 11th hour. It's very ideological.

 

[Thunder 57]

When did this turn in to an Intel thread?

 

[DrMrLordX]

When did this turn in to an Intel thread?

When it became obvious that Intel still won't have competition for Zen6.

 

[511]

When it became obvious that Intel still won't have competition for Zen6.

Nice one but it is not true 🫠🫠 but I guess only time will tell

 

[Joe NYC]

Scale up those factories then - place long term big orders, there - solved it for you. That can't be expensive if they only charge 15-20 per CPU which adds at least 100 to sale price.

It is quite possible TSMC was going to do it on their own (make the investments) in order to attract more customers.

But in the meantime the AI boom started, and most of TSMC capital, facilities were re-purposed to make more of CoWoS packaging.

As of now, it seems like AMD is ramping up the V-Cache at a steady pace. V-Cahce will play a greater role, with more and higher volume products having V-Cache options - Medusa Point, Medusa Halo, in addition to desktop and server.

It is possible that by the time Zen 7 comes around, AMD makes the decision to drop L3 from the main CCD die in premium chiplet products, or even from experimental Zen 6 die.

 

[Joe NYC]

Yea, well they are saying H1 2026 for CWF .... which generally means end of May 2026 in my book. Best info I can find on EPYC Venice is "2026" which I am guessing means end of Q4. Also, based on the fact that the first wafers seem to be EPYC and not desktop, either desktop is later, or desktop is N3P. I have heard little to no info on Diamond Rapids.

If both AMD and TSMC staged the PR event announcing Zen 6 (EPYC) is the leading product on N2, it does not make a lot of sense for this chip to ship as ~ #10 product on N2 (almost a year later), rather than as #1 or close to #1.

 

[Thunder 57]

It is quite possible TSMC was going to do it on their own (make the investments) in order to attract more customers.

But in the meantime the AI boom started, and most of TSMC capital, facilities were re-purposed to make more of CoWoS packaging.

As of now, it seems like AMD is ramping up the V-Cache at a steady pace. V-Cahce will play a greater role, with more and higher volume products having V-Cache options - Medusa Point, Medusa Halo, in addition to desktop and server.

It is possible that by the time Zen 7 comes around, AMD makes the decision to drop L3 from the main CCD die in premium chiplet products, or even from experimental Zen 6 die.

No way AMD srops L3 from the main die. It's one of their biggest advantages over Intel (that I see).

 

[moinmoin]

No way AMD srops L3 from the main die. It's one of their biggest advantages over Intel (that I see).

V-cache is an extension of it. The few additional cycles that L3$ extension costs is due to the increase in total size, not because it is not on the main die.

But yeah, I don't see AMD doing a die that relies completely on v-cache for L3$.

 

[Kepler_L2]

https://twitter.com/x/status/1919702960273326131

Looks like Venice and Medusa may share the same N2 12C CCD after all

 

[OneEng2]

https://twitter.com/x/status/1919702960273326131

Looks like Venice and Medusa may share the same N2 12C CCD after all

Link didn't work for me, but I'll take your word for it .

If that is the case, then:

• Desktop is assured to be N2 CCD
• Likely 192c for the high performance Turin
• Turin D @ ~240-288 Zen 6c cores (20-24 CCD's)?

 

[adroc_thurston]

It's one of their biggest advantages over Intel (that I see).

The advantage is that AMD L3 doesn't suck.
Otherwise 3D stacking penalty for LLCs is like 4 cycles.