Question Zen 6 Speculation Thread

[Tigerick]

that's... made up? why are you confident in N3 for 12C classic? why is there a random jump from HP to HD in 192->256? reduce+reuse is like the whole motto of chiplets.

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process. Plus my source told me long time ago.

HP and HD are same die just different power TDP. Some of the power analysis are based on my calculation in AMD ARM threads. Not confirm but pretty sure...

 

[Joe NYC]

Here is the breakdown of Venice SP7 and SP8:

1. SP8: 96-core (N3P, 8x12-core, 384MB) + 1 IOD 8-channel
2. SP8: 128-core HP (N2, 4x32-core, 512MB) + 1 IOD 8-channel
3. SP7: 192-core HP (N2, 6x32-core, 768MB) + 2 IOD 16-channel
4. SP7: 256-core HD (N2, 8x32-core, 1024MB) + 2 IOD 16-channel

The N3P 12 core highly unlikely

And the number of CCDs, memory channels and IODs has no consistency.

 

[adroc_thurston]

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process

?

 

[511]

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process. Plus my source told me long time ago.

AMD Publicly said Venice is N2

 

[jpiniero]

AMD Publicly said Venice is N2

Which is why the rumors that client doesn't use the server die anymore sounds about right.

 

[Tigerick]

AMD Publicly said Venice is N2

Yep, since both 8x12 or 3x32 will net total 96 cores, I am putting both options. If using 32-core, we might not get high boost clock, so..

 

[LightningZ71]

You're forgetting that there are "die recovery options" where they use dice that have one or more failed cores. 4 x 24 enabled core die works for 96 core products. I just don't expect to see that.

 

[fastandfurious6]

AMD Publicly said Venice is N2

referring to the joint TSMC-AMD press release?

they wouldn't specify N2X in that case, they probably mean N2-node-family

 

[511]

referring to the joint TSMC-AMD press release?

they wouldn't specify N2X in that case, they probably mean N2-node-family

Here is the TSMC Roadmap N2X is H2 27 HVM.
N2Pi s H2 26 HVM if AMD wants to launch product next year it is vanilla N2.

 

[fastandfurious6]

hmmm but the info is zen6 = n2x release in 2026

also I see N3C??? how is it economically viable to make so many new nodes per year

 

[511]

hmmm but the info is zen6 = n2x release in 2026

Info is Zen 6 is N2 I only remember one guy claiming this MLID.

also I see N3C??? how is it economically viable to make so many new nodes per year

They are not entirely new nodes few are what we call a Plus and some are feature expansion.

 

[OneEng2]

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process. Plus my source told me long time ago.

HP and HD are same die just different power TDP. Some of the power analysis are based on my calculation in AMD ARM threads. Not confirm but pretty sure...

It would not surprise me at all for client to be on N3P while DC is on N2.

AMD Publicly said Venice is N2

... and I suspect that all variants of DC EPYC Zen 6 will be N2.

What I DON'T believe is that AMD will lower their core count or memory bandwidth per CCD.

With that in mind, I don't see AMD going below 1 memory channel per CCD. So 1 IOD = 4 memory channels and 4 CCD's makes perfect sense to me.

It ALSO doesn't make sense to me to create a 32c CCD in this arrangement since the bandwidth per core would be cut in half from Turin. Also, as I have stated and shown repeatedly, a 32c CCD would be very large compared to last generation (around double).

There are many reasons I have listed above to believe that the CCD core counts will not double as is being suggested. The only reason that I can see for people to believe in the 32c CCD is that the want it to be true.

I am just seeing it to be highly impractical from several points of engineering.

Perhaps I am missing something?

 

[fastandfurious6]

nahhh bruh no way N3P so late in 2026, amd is gonna lose the game if thats the case

all zen6 gonna be N2(X)

 

[Joe NYC]

It would not surprise me at all for client to be on N3P while DC is on N2.

I think the point you are missing is that it is only the chiplet based CPUs that will be N2. In other words, premium products: Server, premium desktop, premium notebook.

For premium products the small cost difference matters less top tier performance.

For lower tier products in consumer sparce, AMD will likely have monolithic designs, and those could be N3P

... and I suspect that all variants of DC EPYC Zen 6 will be N2.

What I DON'T believe is that AMD will lower their core count or memory bandwidth per CCD.

With that in mind, I don't see AMD going below 1 memory channel per CCD. So 1 IOD = 4 memory channels and 4 CCD's makes perfect sense to me.

It ALSO doesn't make sense to me to create a 32c CCD in this arrangement since the bandwidth per core would be cut in half from Turin. Also, as I have stated and shown repeatedly, a 32c CCD would be very large compared to last generation (around double).

The core count for highest core CPU would go from 192 to 256, which is +33%. But 2 things will happen:
- Memory speeds will go up, including introduction of MrDIMM by the time Venice launches
- L3 per core doubles, with 32 cores being in the same pool (which helps the hit rate further).

There are many reasons I have listed above to believe that the CCD core counts will not double as is being suggested. The only reason that I can see for people to believe in the 32c CCD is that the want it to be true.

I am just seeing it to be highly impractical from several points of engineering.

Perhaps I am missing something?

Core counts double per CCD, not per CPU package. Number of CCDs goes down from 12 (Turin Dense) to 8 (Venice Dense) - if my understanding is correct.

 

[yuri69]

Core counts double per CCD, not per CPU package.

AFAIK we are still waiting for a proper Zen 5 CCD analysis. It remains to be answered how well the 8c vs 16c CCD scales.

 

[Joe NYC]

AFAIK we are still waiting for a proper Zen 5 CCD analysis. It remains to be answered how well the 8c vs 16c CCD scales.

Which would not be exactly apples to apples comparison, with number of differences:
- bandwidth limit per CCD
- 2 MB vs. 4 MB L3 cache
- same sized pool for L3 for double the cores

Both are limiting scaling on Zen 5. But with Zen 6
- bandwidth limit per CCD increased
- same 4 MB L3 cache
- the pool for L3 cache scales linearly with cores, which could IMPROVE scaling.

 

[adroc_thurston]

Which would not be exactly apples to apples comparison, with number of differences:
- bandwidth limit per CCD
- 2 MB vs. 4 MB L3 cache
- same sized pool for L3 for double the cores

Both are limiting scaling on Zen 5. But with Zen 6
- bandwidth limit per CCD increased
- same 4 MB L3 cache
- the pool for L3 cache scales linearly with cores, which could IMPROVE scaling.

yeah venice is good stuff.
next.

 

[CakeMonster]

Any info on updated chipset or refreshes for consumer desktop? I guess we we ever get another 2 or 4 more PCIE lanes (at best) it will probably be with Z7...?

 

[adroc_thurston]

Any info on updated chipset or refreshes for consumer desktop?

You get Zen6 and moar of it.

we we ever get another 2 or 4 more PCIE lanes (at best) it will probably be with Z7...?

Whenever AM5 gets replaced indeed.

 

[OneEng2]

think the point you are missing is that it is only the chiplet based CPUs that will be N2. In other words, premium products: Server, premium desktop, premium notebook.

For premium products the small cost difference matters less top tier performance.

For lower tier products in consumer sparce, AMD will likely have monolithic designs, and those could be N3P

I think that AMD will continue to use chiplet design for desktop and server. It is possible that like Strix Point, there will be a monolithic die for that specific market (utilizing both P and E cores).

There is reportedly only a 15% transistor density gain from N3E to N2. I suspect that from N3P to N2 it may well be even less.

It is my belief that if AMD believes they can make a processor that is competitive with Intel on N3P, they will certainly do it. Zen 5 desktop could have been produced on N3E (obviously as it WAS used on Turin D). I see no business reason for AMD to pay for N2 if they can best Intel with N3P.

The core count for highest core CPU would go from 192 to 256, which is +33%. But 2 things will happen:
- Memory speeds will go up, including introduction of MrDIMM by the time Venice launches
- L3 per core doubles, with 32 cores being in the same pool (which helps the hit rate further).

Turin utilized a single IOD that connected 12 CCD's (each having 16 cores) for 192 cores. That IOD also connected 12 memory channels of DDR6000.

Assuming that Venice supports 16 channels of MR-DIMM 6400, the bandwidth would go from 576 to 1024Gb/sec. Not quite double, so those speculating that AMD will double the cores per CCD on Venice Dense get a point for their side.

With your contention that the L3 will double, the die size goes crazy though. Cache doesn't scale well in density. It is almost certain that Zen 6 will increase in transistor count from Zen 5. Moving from a 16 core CCD to a 32 core CCD (for dense) would likely more than double the current 86mm2 die ... so lets say 180-200mm2. That is a shockingly huge die on a shockingly expensive process.

You are estimating a 256 core Venice D. If the current rumor is correct that each IOD will handle 4 CCD's, then a 4 IOD processor would have 16 core CCD's and 16 memory channels.

That actually sounds about right to me (unlike the 32 core speculation).

ore counts double per CCD, not per CPU package. Number of CCDs goes down from 12 (Turin Dense) to 8 (Venice Dense) - if my understanding is correct.

See above. I think if the rumors of the 4 channel memory, 4 CCD modular IOD for Venice is correct, then we will be looking at a 256c Venice D using 16 core CCD's.

The non-D Venice would then likely use the 12 core CCD (might even share the one from the desktop) giving it a total of 4 IOD's and 192c of full Zen 6 processors.

If you scale all this down to the SP8 socket that supports 12 DDR5 channels, and assume that the same modular IOD will be used, you get a 3 IOD design. This gives you a 144c non-D Venice and a 192c Venice D.

I can't believe how long we will have to be speculating on this before we find out which of our assumptions were correct .

 

[reaperrr3]

I see no business reason for AMD to pay for N2 if they can best Intel with N3P.

- At the time they had to decide on a process node, they couldn't know for sure whether they can best Intel with N3P or not.
- Wafer price mark-up of N2 vs. N3P is allegedly relatively modest and more or less worth the density and efficiency/clock gains, by the sound of it.
- By using N2, they could possibly best Intel by a larger margin than if they used N3P.
Intel still has some legacy clout left in both mainstream consumer space and the corporate world, AMD would have a better chance of continuing to win mindshare by consistently beating Intel by a healthy margin.

At the very least, the 32c CCD for Venice-D probably needed the density and efficiency gains of N2 anyway.

 

[Joe NYC]

I think that AMD will continue to use chiplet design for desktop and server. It is possible that like Strix Point, there will be a monolithic die for that specific market (utilizing both P and E cores).

There is reportedly only a 15% transistor density gain from N3E to N2. I suspect that from N3P to N2 it may well be even less.

It is my belief that if AMD believes they can make a processor that is competitive with Intel on N3P, they will certainly do it. Zen 5 desktop could have been produced on N3E (obviously as it WAS used on Turin D). I see no business reason for AMD to pay for N2 if they can best Intel with N3P.

I don't think AMD wants to take chances and barely outcompete Intel, AMD wants to crush Intel in the premium segments and relegate Intel to value segments.

As of this current quarter, Year over Year AMD ASPs are up 43%, double digits in QoQ. While Intel is forced to cut prices due to lack of interest from Premium segment buyers. That's where AMD wants to be.

Turin utilized a single IOD that connected 12 CCD's (each having 16 cores) for 192 cores. That IOD also connected 12 memory channels of DDR6000.

Assuming that Venice supports 16 channels of MR-DIMM 6400, the bandwidth would go from 576 to 1024Gb/sec. Not quite double, so those speculating that AMD will double the cores per CCD on Venice Dense get a point for their side.

With your contention that the L3 will double, the die size goes crazy though. Cache doesn't scale well in density. It is almost certain that Zen 6 will increase in transistor count from Zen 5. Moving from a 16 core CCD to a 32 core CCD (for dense) would likely more than double the current 86mm2 die ... so lets say 180-200mm2. That is a shockingly huge die on a shockingly expensive process.

I was surprised by this as well, and this is where V-Cache seems almost a non-brainer. So we will see what really is released. But I suspect 128MB L3 is correct.

You are estimating a 256 core Venice D. If the current rumor is correct that each IOD will handle 4 CCD's, then a 4 IOD processor would have 16 core CCD's and 16 memory channels.

I have not been able to solve this puzzle, but it seems more like 2 IODs with 4 CCD connections each.

If there is a 12 core that is being manufactured on a massive scale, shared from premium laptops to high performance (per thread) servers, I don't see the need for 16 core, which is only 33% core count increment.

That actually sounds about right to me (unlike the 32 core speculation).

The 32 core speculation / leaks have been around for a while, I suspect they are correct.

While, at the same time, nothing on 16 core CCD.

 

[adroc_thurston]

I think if the rumors of the 4 channel memory, 4 CCD modular IOD for Venice is correct

It's not modular, just halves.
Composable I/O is a Navi4C/MI400 gimmick.

 

[eek2121]

my take: Zen 6 - N2P, client announcements at computex, launch in July. Rebrand won’t happen. 11950X, 11900X, etc.

This is based on publically available data. Not a leak or from leaks/rumors.

EDIT: if not N2P, it will be a customized N2 process specific to AMD. (they have done this before)

 

[511]

my take: Zen 6 - N2P, client announcements at computex, launch in July. Rebrand won’t happen. 11950X, 11900X, etc.

This is based on publically available data. Not a leak or from leaks/rumors.

My take Zen 6 is Vanilla N2 if it is N2P it is launching H2 27.