Question Zen 6 Speculation Thread

[Tigerick]

that's... made up? why are you confident in N3 for 12C classic? why is there a random jump from HP to HD in 192->256? reduce+reuse is like the whole motto of chiplets.

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process. Plus my source told me long time ago.

HP and HD are same die just different power TDP. Some of the power analysis are based on my calculation in AMD ARM threads. Not confirm but pretty sure...

 

[Joe NYC]

Here is the breakdown of Venice SP7 and SP8:

1. SP8: 96-core (N3P, 8x12-core, 384MB) + 1 IOD 8-channel
2. SP8: 128-core HP (N2, 4x32-core, 512MB) + 1 IOD 8-channel
3. SP7: 192-core HP (N2, 6x32-core, 768MB) + 2 IOD 16-channel
4. SP7: 256-core HD (N2, 8x32-core, 1024MB) + 2 IOD 16-channel

The N3P 12 core highly unlikely

And the number of CCDs, memory channels and IODs has no consistency.

 

[adroc_thurston]

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process

?

 

[511]

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process. Plus my source told me long time ago.

AMD Publicly said Venice is N2

 

[jpiniero]

AMD Publicly said Venice is N2

Which is why the rumors that client doesn't use the server die anymore sounds about right.

 

[Tigerick]

AMD Publicly said Venice is N2

Yep, since both 8x12 or 3x32 will net total 96 cores, I am putting both options. If using 32-core, we might not get high boost clock, so..

 

[LightningZ71]

You're forgetting that there are "die recovery options" where they use dice that have one or more failed cores. 4 x 24 enabled core die works for 96 core products. I just don't expect to see that.

 

[fastandfurious6]

AMD Publicly said Venice is N2

referring to the joint TSMC-AMD press release?

they wouldn't specify N2X in that case, they probably mean N2-node-family

 

[511]

referring to the joint TSMC-AMD press release?

they wouldn't specify N2X in that case, they probably mean N2-node-family

Here is the TSMC Roadmap N2X is H2 27 HVM.
N2Pi s H2 26 HVM if AMD wants to launch product next year it is vanilla N2.

 

[fastandfurious6]

hmmm but the info is zen6 = n2x release in 2026

also I see N3C??? how is it economically viable to make so many new nodes per year

 

[511]

hmmm but the info is zen6 = n2x release in 2026

Info is Zen 6 is N2 I only remember one guy claiming this MLID.

also I see N3C??? how is it economically viable to make so many new nodes per year

They are not entirely new nodes few are what we call a Plus and some are feature expansion.

 

[OneEng2]

N3P for 12-core will be used for Client and server lineup, there is no need for 12-core to use N2 process. Plus my source told me long time ago.

HP and HD are same die just different power TDP. Some of the power analysis are based on my calculation in AMD ARM threads. Not confirm but pretty sure...

It would not surprise me at all for client to be on N3P while DC is on N2.

AMD Publicly said Venice is N2

... and I suspect that all variants of DC EPYC Zen 6 will be N2.

What I DON'T believe is that AMD will lower their core count or memory bandwidth per CCD.

With that in mind, I don't see AMD going below 1 memory channel per CCD. So 1 IOD = 4 memory channels and 4 CCD's makes perfect sense to me.

It ALSO doesn't make sense to me to create a 32c CCD in this arrangement since the bandwidth per core would be cut in half from Turin. Also, as I have stated and shown repeatedly, a 32c CCD would be very large compared to last generation (around double).

There are many reasons I have listed above to believe that the CCD core counts will not double as is being suggested. The only reason that I can see for people to believe in the 32c CCD is that the want it to be true.

I am just seeing it to be highly impractical from several points of engineering.

Perhaps I am missing something?

 

[fastandfurious6]

nahhh bruh no way N3P so late in 2026, amd is gonna lose the game if thats the case

all zen6 gonna be N2(X)

 

[Joe NYC]

It would not surprise me at all for client to be on N3P while DC is on N2.

I think the point you are missing is that it is only the chiplet based CPUs that will be N2. In other words, premium products: Server, premium desktop, premium notebook.

For premium products the small cost difference matters less top tier performance.

For lower tier products in consumer sparce, AMD will likely have monolithic designs, and those could be N3P

... and I suspect that all variants of DC EPYC Zen 6 will be N2.

What I DON'T believe is that AMD will lower their core count or memory bandwidth per CCD.

With that in mind, I don't see AMD going below 1 memory channel per CCD. So 1 IOD = 4 memory channels and 4 CCD's makes perfect sense to me.

It ALSO doesn't make sense to me to create a 32c CCD in this arrangement since the bandwidth per core would be cut in half from Turin. Also, as I have stated and shown repeatedly, a 32c CCD would be very large compared to last generation (around double).

The core count for highest core CPU would go from 192 to 256, which is +33%. But 2 things will happen:
- Memory speeds will go up, including introduction of MrDIMM by the time Venice launches
- L3 per core doubles, with 32 cores being in the same pool (which helps the hit rate further).

There are many reasons I have listed above to believe that the CCD core counts will not double as is being suggested. The only reason that I can see for people to believe in the 32c CCD is that the want it to be true.

I am just seeing it to be highly impractical from several points of engineering.

Perhaps I am missing something?

Core counts double per CCD, not per CPU package. Number of CCDs goes down from 12 (Turin Dense) to 8 (Venice Dense) - if my understanding is correct.

 

[yuri69]

Core counts double per CCD, not per CPU package.

AFAIK we are still waiting for a proper Zen 5 CCD analysis. It remains to be answered how well the 8c vs 16c CCD scales.

 

[Joe NYC]

AFAIK we are still waiting for a proper Zen 5 CCD analysis. It remains to be answered how well the 8c vs 16c CCD scales.

Which would not be exactly apples to apples comparison, with number of differences:
- bandwidth limit per CCD
- 2 MB vs. 4 MB L3 cache
- same sized pool for L3 for double the cores

Both are limiting scaling on Zen 5. But with Zen 6
- bandwidth limit per CCD increased
- same 4 MB L3 cache
- the pool for L3 cache scales linearly with cores, which could IMPROVE scaling.

 

[adroc_thurston]

Which would not be exactly apples to apples comparison, with number of differences:
- bandwidth limit per CCD
- 2 MB vs. 4 MB L3 cache
- same sized pool for L3 for double the cores

Both are limiting scaling on Zen 5. But with Zen 6
- bandwidth limit per CCD increased
- same 4 MB L3 cache
- the pool for L3 cache scales linearly with cores, which could IMPROVE scaling.

yeah venice is good stuff.
next.

 

[CakeMonster]

Any info on updated chipset or refreshes for consumer desktop? I guess we we ever get another 2 or 4 more PCIE lanes (at best) it will probably be with Z7...?

 

[adroc_thurston]

Any info on updated chipset or refreshes for consumer desktop?

You get Zen6 and moar of it.

we we ever get another 2 or 4 more PCIE lanes (at best) it will probably be with Z7...?

Whenever AM5 gets replaced indeed.