Not if you use revancedNo, it's a MLID video, always with message from his sponsor...
Yeah that makes sense, I think late 2027/early 2028 sounds more akin A16 for Consumer CCDs with A14 being for Zen 7 Dense later on when it comes to mass production and stick to AM5, and then 2029 sees Zen 8 with AM6 & CCDs using A14 SPR (TSMC BSPD).This looks to me like one implementation - of server a chiplet. We can take some clues as to what a client chiplets will look like, but not necessarily the same as server.
So looks like AMD is going up to 2 MB L2 on the main core die (which should have some IPC implications).
And then, they are going from 4 MB per core to 7 MB per core (presumably, if there is 1:1 ratio of cores to cache slices).
So for server variants, these are improvements from current base implementations. If that parallels client (with lower core count, maybe 16), it will also be improvement fro 4MB L3 per core.
But V-Cache currently offers 12 MB L3 per core, so we will see if there is going to be a way to maintain or even increase L3 per core using a different method (or stacking ore cache dies).
Probably but Zen 7 sounds ambitious in a lot of stuff, so do it on AM5 first with sacrificing a bit of performance ala Zen 3 and then Zen 8 can be akin to Zen 4 (with maybe an increase of core count to 16 per CCD). And also to compete against Razor Lake-S.Just my thoughts but Zen 7 is going to AM6 with DDR6 in H2 28
Razer Lake is 2027 iircProbably but Zen 7 sounds ambitious in a lot of stuff, so do it on AM5 first with sacrificing a bit of performance ala Zen 3 and then Zen 8 can be akin to Zen 4 (with maybe an increase of core count to 16 per CCD). And also to compete against Razor Lake-S.
I know, which is why an A16 CCD for Zen 7 may come out as early as Q4 2027 to compete against it on Desktop (and also to trial funky stuff like the Zen 7 3D core).Razer Lake is 2027 iirc
Not gonna happen AMD has 2 year cadence and A16/N2 are kind of same node as A16 is N2 with BSPDN while A14 is entirely different so they need to redo lots of Design and RTL and stuff.I know, which is why an A16 CCD for Zen 7 may come out as early as Q4 2027 to compete against it on Desktop (and also to trial funky stuff like the Zen 7 3D core).
Perhaps. I wouldn't be surprised if was later.Just my thoughts but Zen 7 is going to AM6 with DDR6 in H2 28
Why would A14 be different?Not gonna happen AMD has 2 year cadence and A16/N2 are kind of same node as A16 is N2 with BSPDN while A14 is entirely different so they need to redo lots of Design and RTL and stuff.
Because it's a full node shrink.Why would A14 be different?
So a colossal CPU upgrade with a GPU refresh that should hopefully get a good memory subsystem bump.
There is none.that should hopefully get a good memory subsystem bump.
So there will be a more gfx optimised SoC lower in the stack?There is none.
This isn't the graphics part.
Maybe HXL has it wrong? If it's using desktop CCD then maybe it has non dense cores.How is AMD going to Schedule this is going to be problematic
Apparently the 4C+4D+2LPE is part of IO Die along with GPU and wasted Die Space Unit eand the CCD is shared with Desktop.I
Maybe HXL has it wrong? If it's using desktop CCD then maybe it has non dense cores.
There is none.
This isn't the graphics part.
Dropping from 16cu to 8cu for the gfx part is either an acknowledgement that very few notebooks are being made with just an APU on that segment of the market, or they have unlocked the secret of massively clocking the iGPU massively higher. If you are seeing Strix Point, or for when this was planned, Hawk Point in a notebook, it either has a dGPU with it, or it's a professional business laptop where no one really cares about GFX performance to begin with. The only market that "suffers" is the tiny micro desktops in the Mac mini size. As for being higher clocked, there should be some gain from the node jump, and the 16cu GPU from Strix was heavily held back by memory performance anyway.
The main thing that I see as an issue is that the jump from R7 to R9 is massive. I think that the R7 is under sized in the leak config. I'd like to think that, unless there are several R9 configs, the R7 should have the recovery CCD with like 6-8 cores enabled, and the R9 should be the full fat product.
Few issues Strix Halo is way over priced as of rn those who are fine with 8CU will be fine with 4+4+2 R7.The way I think AMD views this market, regarding GPU is in Medusa Point:
- those who don't care will be ok with 8 CU (probably clocked faster on N3P)
- those who do care but don't care about power - will get it with dGPU
- those who do care and also care about power - Will get the Halo CPU product
I think this is correct. 16CU is such a half way house. It's not good enough to displace discrete, so if most strict point laptops have dedicated GPUs it's wasted silicon cost.The way I think AMD views this market, regarding GPU is in Medusa Point:
- those who don't care will be ok with 8 CU (probably clocked faster on N3P)
- those who do care but don't care about power - will get it with dGPU
- those who do care and also care about power - Will get the Halo CPU product
Not enough supply right now. More chassis and competition hopefully by the time Medusa halo comes round. And higher volume means lower cost per itemFew issues Strix Halo is way over priced as of rn those who are fine with 8CU will be fine with 4+4+2 R7.
It is not, the 16C chip is sold about 500$ in the chinese retail market, so OEMs get it for much lower than this.Few issues Strix Halo is way over priced as of rn those who are fine with 8CU will be fine with 4+4+2 R7.