Eventually yeah, but the standard was released too late to be part of Zen6.
Eventually yeah, but the standard was released too late to be part of Zen6.I didn't think AMD was even going to bother with AMX. SUrely they plan on using APX though?
No? while the fab to feed etc is true you are missing the fact that the wafer margins are going to Intel instead of TSMC also the R&D/Fab Intel has already spent too much that was to catch up to the underinvestment.Hardly.
Intel has more mouths to feed, fab plants to feed, Fab R&D to feed, 18A development to feed (and future nodes), High NA to feed, etc, etc, etc.
Currently, on top of all that, Intel is ALSO feeding TSMC.
My contention is that even if Intel were to go back to being 100% vertically integrated, their cost structure per wafer would be WAY higher than AMD using TSMC (even if they used all N2 for Zen 6).
It is when you're arguing with people that claim to have insider information.Crazy how people speculate in a speculation thread .
Thank you!The only meaningful information I can recall is that one or more of the server parts will be the first off the TSMC N2 line.
Leaks suggest that a new IOD for server will be modular and support 4 CCDs and 4 channels of memory. Since socket SP7 only supports 16 channels, speculation about core counts revolves around a max of 4 IOD's and 16 CCD's for DC.
I don't recall much leakage of information on laptop or desktop.
Honestly, I would look at the other sources in this thread rather than OneEng2 for information. They are speculating on what they think, which is fine of course, but others here have more info so I'd look there if you want to understand what the lineup looks like. Whether you trust them is up to you, but just read the last 5 pages of you'd like picture based on that info rather than the speculative guesses OneEng2 is throwing out. No shade in this post by the way, they are having fun.Thank you!
Another question, has the 12-core compute die been confirmed, or it is still a rumor? If confirmed, even for desktop, i mean "client", or that one is going to stick to 8-core chiplets?
Finally, if its happening across the board, even for desktops, do we expect dual-chiplet variant as well, i mean *950x SKU? Or will AMD be like "this new 12core CPU is in most situations (browsing, games) 10-15 percent faster than your old 16core, give 700 bucks for this SINGLE compute tile product naow?
Are you assuming that all fabs are equal in margin irrespective of operational and geographic variations? A fab is a fab is a fab?No? while the fab to feed etc is true you are missing the fact that the wafer margins are going to Intel instead of TSMC also the R&D/Fab Intel has already spent too much that was to catch up to the underinvestment.
As for Intel feeding TSMC this will soon be down near the year end or early next year.
By confirmed, do you mean publicly disclosed by AMD?Another question, has the 12-core compute die been confirmed, or it is still a rumor?
At Computex 2025 (May 20-23), AMD presented Radeon RX 9060 XT and FSR 4, and previewed Threadripper 9000 and Radeon AI Pro R9700.So any news on Zen6 recently, the desktop parts i mean? Havent paid attention recently at all, dont even know whether there was Computex already.
No? I am well aware of that it's totally dependent on the process cost structure cause the cost of equipment is nearly the same across Intel/TSMC/Samsung.Are you assuming that all fabs are equal in margin irrespective of operational and geographic variations? A fab is a fab is a fab?
Few things first 18A cost structure and from the public info that might not require double patterning for 18A which is huge cause N2 for sure is double patterned.What makes you think Intel will have any positive margins. It's possible they might just lose less. It all depends on their cost of production, on which we have no clue.
Well TSMC's most US fab worker are Taiwanese not to mention they had large issues due to culture and other stuff something Intel hasn't had to deal with it is surely expensive to build in US vs Taiwan but TSMC is exaggerating a bit there was a Techinsight article regarding the fab cost and iirc it was 7-10% more expensive than to build fabs it is somewhere in between thatTSMC (USA) is already claimed to be 30%+ more expensive. That directly translates to an equivalent Taiwanese fab margin. Where these trade wars end is anyone's guess, but that is probably the only way to have pricing parity, at least in the US. The wider world will go to the cheapest supplier, and in turn, the end products will be more competitive.
OK. While i adressed my post at them, as they responded to my previous post, it was more of question for everyone here, willing to answer.Honestly, I would look at the other sources in this thread rather than OneEng2 for information. They are speculating on what they think, which is fine of course, but others here have more info so I'd look there if you want to understand what the lineup looks like. Whether you trust them is up to you, but just read the last 5 pages of you'd like picture based on that info rather than the speculative guesses OneEng2 is throwing out. No shade in this post by the way, they are having fun.
It's in the previous 5 pages. You can read them if you'd like an answer. I've also posted summaries.OK. While i adressed my post at them, as they responded to my previous post, it was more of question for everyone here, willing to answer.
I mean, i would appreciate, even if the others, who you say might have more info, answered those questions. I am all for open debate.
Thanks, will doIt's in the previous 5 pages. You can read them if you'd like an answer. I've also posted summaries.
So the info that the 9950X successor is basically 2x 12C Zen6 and new IOD with 4x LPE Zen6 (and NPU & iGPU) is speculation then as I understand it.Honestly, I would look at the other sources in this thread rather than OneEng2 for information. They are speculating on what they think, which is fine of course, but others here have more info so I'd look there if you want to understand what the lineup looks like. Whether you trust them is up to you, but just read the last 5 pages of you'd like picture based on that info rather than the speculative guesses OneEng2 is throwing out.
2X LPE cores and I think those are 5C not Zen 6 maybe I am wrong about the 5C part.So the info that the 9950X successor is basically 2x 12C Zen6 and new IOD with 4x LPE Zen6 (and NPU & iGPU) is speculation then as I understand it.
But what is the alternative speculation? It’s not obvious from the last 5 pages that you mentioned I think.
So the info that the 9950X successor is basically 2x 12C Zen6 and new IOD with 4x LPE Zen6 (and NPU & iGPU) is speculation then as I understand it.
But what is the alternative speculation? It’s not obvious from the last 5 pages that you mentioned I think.
The LP cores have architectural changes from Classic/Dense cores and Zen5/6 have the same ISA support so technically they could call it either Zen5LP or Zen6LP.2X LPE cores and I think those are 5C not Zen 6 maybe I am wrong about the 5C part.
From 0 TOPS to 40 TOPS ♾️ performance upgrade(40/0).Would be nice to see them double the iGPU from 2CU to 4, but gotta have that NPU!
From 0 TOPS to 40 TOPS ♾️ performance upgrade(40/0).
If they don't mess up the encode decode AMD barely caught with Intel in this department with RDNA 4.I'm still waiting for something I use to make use of an NPU. I understand that's where things are headed so I get why it's there. And to be fair two more CU's doesn't do much anyway. As long as they have all of the relevant encode/decode this is more important.
Why do you think it’s 2x LPE instead of 4x? For comparison, Nova Lake-S will be using 4x according to latest rumors/leaks.2X LPE cores and I think those are 5C not Zen 6 maybe I am wrong about the 5C part.
AMD's roadmaps and intels are different. They're different companies and have different cores and strategies.Why do you think it’s 2x LPE instead of 4x? For comparison, Nova Lake-S will be using 4x according to latest rumors/leaks.
If you think the 30K is bad, word on the street is that A14 will be 45K/wafer.
One can't rule the classic AMD cheapo approach out, hence 8c CCDs on a 3nm process using a different 5nm IOD.But what is the alternative speculation? It’s not obvious from the last 5 pages that you mentioned I think.
Yes, but do you have access to AMD’s roadmap w.r.t. LPE cores?AMD's roadmaps and intels are different. They're different companies and have different cores and strategies.
MLID expecting high performance (like zen 3 core) from LP coresAre you e.g. expecting that AMD’s LPE cores will have much higher performance per core than Intel?