Question Zen 6 Speculation Thread

[Fjodor2001]

MLID expecting high performance (like zen 3 core) from LP cores

Functionally you just need power efficient cores to handle back ground OS tasks & wake up from sleep etc.
Basically extend battery life for low usage scenarios

From what was mentioned in the thread previously, at least the 4 Intel cores could handle tasks like typing an email, reading a web page, or watching a video, without having to wake up the big / high performance cores.

I think it would be very useful to aim for that, since many users spend a lot of time doing such tasks. So power consumption (and battery life where applicable) can be improved a lot if the LPE cores can handle such use cases by themselves (with assistance from he iGPU which is also on the IOD).

 

[511]

From what was mentioned in the thread previously, at least the 4 Intel cores could handle tasks like typing an email, reading a web page, or watching a video, without having to wake up the big / high performance cores.

I think it would be very useful to aim for that, since many users spend a lot of time doing such tasks. So power consumption (and battery life where applicable) can be improved a lot if the LPE cores can handle such use cases by themselves (with assistance from he iGPU which is also on the IOD).

Well Zen 5 and Skymont are different arch and Skymont cluster is a 4C Cluster while 5C is a shrinked down version of Zen 5 cores with 2T per core so the threads will be the same.

For these taks you want your leakage to be as low as possible and you don't want peak ST performance to sustain them you want these core to be as smaller and less leaky as possible.

Btw NVL will use arctic wolf with APX for full fat ISA compatibility so the SoC tile can either be I3/18A.

 

[MS_AT]

Also, from was discussed earlier in this thread, 2 LPE cores was considered too weak to do their intended job for Intel so they bumped it to 4, and also used higher performing cores. Is there any reason to assume the same should not be true for AMD? Are you e.g. expecting that AMD’s LPE cores will have much higher performance per core than Intel?

Is there any reason to assume AMD and INTEL LPE cores share anything between the common acronym?

From what was mentioned in the thread previously, at least the 4 Intel cores could handle tasks like typing an email, reading a web page, or watching a video, without having to wake up the big / high performance cores.

I would not expect LPE cores to be used for anything that requires interactivity from the user. So watching videos, is ok, browsing the net not so much. Also notice, CCD<->IOD link will consume considerably less power if we are to judge by Halo's example and you will not notice the difference in the power consumption of few Watts due to power supply inefficiencies. On mobile, since IOD is supposed to have some normal cores too, then handing over shouldn't be a problem.

 

[StefanR5R]

Is there any reason to assume AMD and INTEL LPE cores share anything between the common acronym?

They don't even share the acronym.

 

[OneEng2]

It is when you're arguing with people that claim to have insider information.

Since this is a speculation thread, AND no concrete evidence has been produced, I'll "argue" with whomever I choose to as my speculation is just as good as the next guys. Furthermore, the claims are not consistent with AMD's prior behavior and would indicate a departure from a philosophy that we have seen AMD use.

I think more than a one line snarky answer from "people that claim to have insider information" is needed don't you think?

Thank you!

Another question, has the 12-core compute die been confirmed, or it is still a rumor? If confirmed, even for desktop, i mean "client", or that one is going to stick to 8-core chiplets?

Finally, if its happening across the board, even for desktops, do we expect dual-chiplet variant as well, i mean *950x SKU? Or will AMD be like "this new 12core CPU is in most situations (browsing, games) 10-15 percent faster than your old 16core, give 700 bucks for this SINGLE compute tile product naow?

12 cores is a leak. From here: https://www.tomshardware.com/pc-com...desktop-processors-may-feature-up-to-24-cores

Toms reported this.

Keep in mind that there would likely be CCD variants lower than 12c done simply for binning reasons when a defect disables one of a 2 core complex (sharing L2).

The assumption that there would then be a 24c variant is speculation based on AMD's previous designs.

Honestly, I would look at the other sources in this thread rather than OneEng2 for information. They are speculating on what they think, which is fine of course, but others here have more info so I'd look there if you want to understand what the lineup looks like. Whether you trust them is up to you, but just read the last 5 pages of you'd like picture based on that info rather than the speculative guesses OneEng2 is throwing out. No shade in this post by the way, they are having fun.

Yes, but my speculative guesses come with information that backs up the speculation. No trust is needed, just a bit of reasoning. Additionally, I post links to actual information when it is available.

When this all works itself out, I may well be proven wrong, but in a speculation thread, I think that well founded speculation is good discussion. Derailing the good discussion with snarky one liners (not you btw) with no reasoning or proof isn't helpful IMO.

Why do you think it’s 2x LPE instead of 4x? For comparison, Nova Lake-S will be using 4x according to latest rumors/leaks.

It's a good question. In fact, another good question would be how is AMD planning on combating the "core wars" advertising? It reminds me of P4 days when the "Mhz wars" raged. It was hard to get people off of the metric that had been ingrained for decades as the metric for performance. AMD finally managed to overcome the problem with model numbers.

Core counts are another problem for AMD IMO. How do you now expect people to understand that 24 AMD cores is better than 52 Intel cores (for the many unfortunate people who aren't part of this forum ).

As for the technical answer, I think that it is entirely possible that 2 Zen 6c LP cores would work as well as 4 Intel LP cores for the intended purposes (4 low priority, low compute threads being handled).

Yes, but do you have access to AMD’s roadmap w.r.t. LPE cores?

Also, from was discussed earlier in this thread, 2 LPE cores was considered too weak to do their intended job for Intel so they bumped it to 4, and also used higher performing cores. Is there any reason to assume the same should not be true for AMD? Are you e.g. expecting that AMD’s LPE cores will have much higher performance per core than Intel?

Possibly so due to SMT.

I do NOT expect AMD to branch their architecture as Intel has for P and E and LP cores. This hasn't been their philosophy to date, and I don't expect it to be in the future for a number of reasons.

 

[Thunder 57]

Since this is a speculation thread, AND no concrete evidence has been produced, I'll "argue" with whomever I choose to as my speculation is just as good as the next guys. Furthermore, the claims are not consistent with AMD's prior behavior and would indicate a departure from a philosophy that we have seen AMD use.

I think more than a one line snarky answer from "people that claim to have insider information" is needed don't you think?

12 cores is a leak. From here: https://www.tomshardware.com/pc-com...desktop-processors-may-feature-up-to-24-cores

Toms reported this.

Keep in mind that there would likely be CCD variants lower than 12c done simply for binning reasons when a defect disables one of a 2 core complex (sharing L2).

The assumption that there would then be a 24c variant is speculation based on AMD's previous designs.

Yes, but my speculative guesses come with information that backs up the speculation. No trust is needed, just a bit of reasoning. Additionally, I post links to actual information when it is available.

When this all works itself out, I may well be proven wrong, but in a speculation thread, I think that well founded speculation is good discussion. Derailing the good discussion with snarky one liners (not you btw) with no reasoning or proof isn't helpful IMO.

It's a good question. In fact, another good question would be how is AMD planning on combating the "core wars" advertising? It reminds me of P4 days when the "Mhz wars" raged. It was hard to get people off of the metric that had been ingrained for decades as the metric for performance. AMD finally managed to overcome the problem with model numbers.

Core counts are another problem for AMD IMO. How do you now expect people to understand that 24 AMD cores is better than 52 Intel cores (for the many unfortunate people who aren't part of this forum ).

As for the technical answer, I think that it is entirely possible that 2 Zen 6c LP cores would work as well as 4 Intel LP cores for the intended purposes (4 low priority, low compute threads being handled).

Possibly so due to SMT.

I do NOT expect AMD to branch their architecture as Intel has for P and E and LP cores. This hasn't been their philosophy to date, and I don't expect it to be in the future for a number of reasons.

You would be one of the people that @igor_kavinski would fire.

 

[igor_kavinski]

You would be one of the people that @igor_kavinski would fire.

For what? For speculating?

 

[Thunder 57]

For what? For speculating?

Sure, let's go with that.

 

[Abwx]

.

Core counts are another problem for AMD IMO. How do you now expect people to understand that 24 AMD cores is better than 52 Intel cores (for the many unfortunate people who aren't part of this forum ).

Price = performance.

 

[StefanR5R]

Keep in mind that there would likely be CCD variants lower than 12c done simply for binning reasons when a defect disables one of a 2 core complex (sharing L2).

Level 2 cache is core-private. In Zen 1...5, cores can disabled one by one.

I do NOT expect AMD to branch their architecture as Intel has for P and E and LP cores. This hasn't been their philosophy to date, and I don't expect it to be in the future for a number of reasons.

Is it useful to consider Intel's two architectures as branches, or aren't they nowadays better characterized as two mostly independent development lines? I don't remember what the common ancestor of "Core" and "Atom" was.

AMD on the other hand introduced configurations into their core microarchitecture, starting with Zen 5. (Different FP and vector pipelines in different product segments, maybe more.) I expect that they will reconfigure the core microarchitecture even more in order to scale down to a lower power variant. (Let's keep in mind though that a "low power island" will also depend a lot on uncore smarts.)

In the past, some wondered whether or not AMD would re-introduce their "cat core" microarchitecture, but this apparently won't happen.

 

[Abwx]

I don't remember what the common ancestor of "Core" and "Atom" was.

Pentium Pro for Core (OoO) and Pentium for Atom (InO).

 

[OneEng2]

Price = performance.

Yes, but how much of that is the PERCEPTION of performance? How would the average consumer know how much performance exists in a specific chip?

On a side note from here: https://www.tomshardware.com/tech-i...ust-deliver-50-percent-to-get-the-green-light

This is what I have been saying for some time (you have to make money making the CPU. It's not enough for it to be performant).

Now there is still lots of wiggle room here. How do they calculate gross margin? Does 50% cover SG&A and other non direct costs? What price do they need to sell at to get 50%? Will the market bear that price?

Still, I think this is a good sign for Intel.

 

[OneEng2]

Level 2 cache is core-private. In Zen 1...5, cores can disabled one by one.

While it is possible, I still think it likely that AMD would keep things at even numbers. It makes for a mess when you have 50 different part numbers .

 

[LightningZ71]

I think that LPE cores are going to make the most sense and have the most impact once they arrive on nodes that have whatever variation of FinFlex is implemented there. it's not enough to just remove the cell padding, being able to adjust the individual transistor types is needed to maximize their benefit. On what we expect to replace Kraken Point and Strix Point in the next cycle, I suspect we'll see an N3 family litho process with not just compact cores, but LP cores with short fins as well.

 

[LightningZ71]

Yes, but how much of that is the PERCEPTION of performance? How would the average consumer know how much performance exists in a specific chip?

On a side note from here: https://www.tomshardware.com/tech-i...ust-deliver-50-percent-to-get-the-green-light

This is what I have been saying for some time (you have to make money making the CPU. It's not enough for it to be performant).

Now there is still lots of wiggle room here. How do they calculate gross margin? Does 50% cover SG&A and other non direct costs? What price do they need to sell at to get 50%? Will the market bear that price?

Still, I think this is a good sign for Intel.

In the end, as long as you can cover ALL of the variable costs of production (consumable materials, man hours of labor, consumed electricity, etc) and then any additional amount towards the fixed costs (facility lease costs, property taxes, facility maintenance costs, mortgage, equipment base rental/lease, etc.) it is in your best interests to produce a product. Yes, you will still be losing money if you can't cover ALL of your fixed costs, but you bleed more slowly.

 

[Joe NYC]

Since this is a speculation thread, AND no concrete evidence has been produced, I'll "argue" with whomever I choose to as my speculation is just as good as the next guys. Furthermore, the claims are not consistent with AMD's prior behavior and would indicate a departure from a philosophy that we have seen AMD use.

I think more than a one line snarky answer from "people that claim to have insider information" is needed don't you think?

12 cores is a leak. From here: https://www.tomshardware.com/pc-com...desktop-processors-may-feature-up-to-24-cores

Toms reported this.

No, it was MLID, Chiphell

Keep in mind that there would likely be CCD variants lower than 12c done simply for binning reasons when a defect disables one of a 2 core complex (sharing L2).

I don't think that's called CCD variant if it is identical CCD with some cores disabled.

 

[igor_kavinski]

On a side note from here: https://www.tomshardware.com/tech-i...ust-deliver-50-percent-to-get-the-green-light

That kind of focus could end up killing some promising projects for enthusiasts, is what I'm worried about. I would prefer that they do a proper analysis of what their customers want and give it to them at a price the customers would love to pay, like for example, a quad channel HEDT platform using consumer CPUs instead of creating a separate CPU line that won't sell that much due to much higher prices.

On the other hand, I hope LBT forces them to go through the inventory of their shelved or unreleased products, investigate their market potential and do the minimum but necessary development to release their improved versions.

 

[OneEng2]

No, it was MLID, Chiphell



I don't think that's called CCD variant if it is identical CCD with some cores disabled.

For the first two, link please?

For the 2nd, I agree. Poor choice of words. Should have said product variants. My point is still true though. Even if AMD CAN isolate a single core that has a defect, it wouldn't make any sense to sell 24 variants of Zen 6 with core counts from 1 to 24 (not to mention the flavors of those based on how many cores on each CCD are good).

 

[branch_suggestion]

Z6 is a more premium product than Z5 no matter how you cut it, they use a lot of different supply chains and Z6 parts need another packaging step.
Logically Z6 can spare no expense for the pursuit of performance, as Z5 can remain as the more affordable option as they share the same sockets.
If with N2, 50% more cores and the new uncore and packaging they can get enough performance to bump the pricing up a tier, then Z5 can remain with only modest discounts to fit in the cost structure.
It is all up to Intel to disrupt this plan.

 

[Joe NYC]

For the first two, link please?

Link to the sources of the rumors / leaks were right in the Tom's article you linked.

For the 2nd, I agree. Poor choice of words. Should have said product variants. My point is still true though. Even if AMD CAN isolate a single core that has a defect, it wouldn't make any sense to sell 24 variants of Zen 6 with core counts from 1 to 24 (not to mention the flavors of those based on how many cores on each CCD are good).

12, 10 and Zen 6 CPUs are likely form 12c die.

It's quite possible that AMD does not release smaller core count for Zen 6 desktop, and instead drops prices on 6 and 8 core Zen 5 to serve the segment. Hopefully, they get an upgraded IO dies.

Edit: looks like @branch_suggestion posted similar comment.

 

[Thunder 57]

Link to the sources of the rumors / leaks were right in the Tom's article you linked.



12, 10 and Zen 6 CPUs are likely form 12c die.

It's quite possible that AMD does not release smaller core count for Zen 6 desktop, and instead drops prices on 6 and 8 core Zen 5 to serve the segment. Hopefully, they get an upgraded IO dies.

Edit: looks like @branch_suggestion posted similar comment.

The upgraded I/O die has long been rumored to be probably the biggest upgrade with Zen 6. There's no doubt the old I/O die currently in use is holding Zen 5 back. Other than that I think updated decoders would be nice. C&C found that any one thread is still limited to 4 decode and only with SMT can you possibly use them all. Four wide decode has been there since Zen 1. Also a bump in L2 cache size might be nice but I don't expect that just yet. AMD's L3 cache is so much better than Intel's that an L2 miss doesn't hurt as much.

 

[Joe NYC]

The upgraded I/O die has long been rumored to be probably the biggest upgrade with Zen 6. There's no doubt the old I/O die currently in use is holding Zen 5 back. Other than that I think updated decoders would be nice. C&C found that any one thread is still limited to 4 decode and only with SMT can you possibly use them all. Four wide decode has been there since Zen 1. Also a bump in L2 cache size might be nice but I don't expect that just yet. AMD's L3 cache is so much better than Intel's that an L2 miss doesn't hurt as much.

Ideal situation would be for AMD to be able to share the new desktop IO Die between Zen 6 and Zen 5 (Strix Halo CCDs) if these were designed to have compatible connectivity.

This would follow AMD strategy of fewest Lego pieces able to address greatest market potential.

 

[basix]

Yeah, I would not mind to get an N3P IOD together with a quite fast iGPU on desktop SKUs

Any differences of mobile and desktop requirements (e.g. number of GPU CU, number of PCIe lanes, number of LP-Zen Cores, NPU size) could be delivered via salvaging the IOD = Better yields.
And you automatically get the xxxxG APUs for desktop for "free" (no additional design). And USB4 can be traded with PCIe lanes: Mobile features more USB4 ports and desktop more PCIe lanes.

This concept somehow aligns well with the rumor about only 8CU on Medusa Point. Saving cost. Use 8CU for mobile parts and 6CU for desktop parts (but potentially cranked up clockrates) would sound good to me.

 

[DrMrLordX]

I think more than a one line snarky answer from "people that claim to have insider information" is needed don't you think?

You're using arguably-torturous deduction to reason with someone who claims to be looking at a spec sheet. Watching the two of you go back and forth is absurd. Leaks probably don't belong in a speculation thread anyway.

So again either accept what the leakers are saying as canon or simply tell them "you can't prove it so you have no argument" and then speculate with someone else who wants to predict the future.

 

[511]

Yeah, I would not mind to get an N3P IOD together with a quite fast iGPU on desktop SKUs

Hold your horses it is a N4C IOD and the packing should be similarish to Intel Foveros they are using interposer afaik for halo.

Any differences of mobile and desktop requirements (e.g. number of GPU CU, number of PCIe lanes, number of LP-Zen Cores, NPU size) could be delivered via salvaging the IOD = Better yields.
And you automatically get the xxxxG APUs for desktop for "free" (no additional design). And USB4 can be traded with PCIe lanes: Mobile features more USB4 ports and desktop more PCIe lanes.

This concept somehow aligns well with the rumor about only 8CU on Medusa Point. Saving cost. Use 8CU for mobile parts and 6CU for desktop parts (but potentially cranked up clockrates) would sound good to me.

The problem is the Nova Lake has Integrated TB5 this one doesn't require PD and retimers it's just plug and play for OEM and with Xe4 Media engine with professional Codec. AMD lags against Intel In this department their motherboard doesn't even get premium feature.
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