IO for both sides has been pretty abysmal forever. IMO the PCI lanes should be doubled. Fast USB gadgets are a thing. Multiple high speed SSDs are a thing, even in a machine with multiple PCIe devices.
I know this was discussed in the context of client. But I point out that AMD is doing so in server.While it [ = disabling cores at a granularity of 1] is possible, I still think it likely that AMD would keep things at even numbers. It makes for a mess when you have 50 different part numbers .
Strix Halo's die-to-die interconnect is logically almost unaltered to Granite Ridge's and Turin's. I expect them to improve on that in Medusa, i.e. make it wider or/and clock it higher. (Might nevertheless be backwards compatible with Strix Halo's pinout, width, speeds, and power states though, but such backwards compatibility has its cost.)Ideal situation would be for AMD to be able to share the new desktop IO Die between Zen 6 and Zen 5 (Strix Halo CCDs) if these were designed to have compatible connectivity.
Zen 4 Ryzen/EYPC/Instinct was the last time AMD stuck with the LEGO® principle. They abandoned it in Zen 5: They have different 8c CCDs for Granite Ridge, Turin, and Strix Halo (Zen 5 thread reference). Of course they are not from-the-ground-up different by any means, but they are not anymore mere different bins at the end of the same conveyor belt.This would follow AMD strategy of fewest Lego pieces able to address greatest market potential.
In desktop computers, it's IMO OK to provide many PCIe/USB/SATA lanes by means of the southbridge, which for a long time now is a PCIe switch with added USB and SATA controllers. However, I find two faults elsewhere:IO for both sides has been pretty abysmal forever. IMO the PCI lanes should be doubled. Fast USB gadgets are a thing. Multiple high speed SSDs are a thing, even in a machine with multiple PCIe devices.
Why not? For comparison, I've got a friend who has a fanless 10+ year old Intel M-5Y10 2C/4T 800/2000Mhz laptop at 4.5W TDP and you can even browse the web perfectly fine on that. Sure a more modern CPU renders the page a bit quicker, but it's actually not that bad. And once the page has been rendered and you're just reading it or scrolling a bit, it does not require much performance.I would not expect LPE cores to be used for anything that requires interactivity from the user. So watching videos, is ok, browsing the net not so much.
– In this day and age of PCIe v3, v4, v5, it makes sense to attach devices with fewer lanes per device, so that the available lane count and board space can be used more flexibly and effectively. But device makers and board makers block each other from going in this direction.
2 or 4 would be my guesstimate, depending on what the performance per core will be and what kind of low performance use case we're talking about. And as I said, big / performance cores might have to be awoken briefly from time to time to handle spikes.So it's settled then: Two low-power cores should be plenty for what they need to do.
The memory controller is on the CPU; they couldn't make a quad channel platform for a consumer CPU, because they only have a dual channel memory controller on the die.That kind of focus could end up killing some promising projects for enthusiasts, is what I'm worried about. I would prefer that they do a proper analysis of what their customers want and give it to them at a price the customers would love to pay, like for example, a quad channel HEDT platform using consumer CPUs instead of creating a separate CPU line that won't sell that much due to much higher prices.
On the other hand, I hope LBT forces them to go through the inventory of their shelved or unreleased products, investigate their market potential and do the minimum but necessary development to release their improved versions.
Once their engineers are on board with the idea and they get the green signal, hopefully they can figure something out with the shortest time to market.The memory controller is on the CPU; they couldn't make a quad channel platform for a consumer CPU, because they only have a dual channel memory controller on the die.
it's on IOD for ZEN4/5 and 6 as wellThe memory controller is on the CPU; they couldn't make a quad channel platform for a consumer CPU, because they only have a dual channel memory controller on the die.
They were talking about Intel, or what they want Intel to be doing. (In an AMD thread.)It's 2025 and people in these threads don't know how AMD cpus are organized? really?
AMD/Intel thread are way interchangeable tbf it happens in Intel thread as well we should make Zen6/Nova Lake combined threadThey were talking about Intel, or what they want Intel to be doing. (In an AMD thread.)
He was talking about Intel, as was I in my response 🙂It's 2025 and people in these threads don't know how AMD cpus are organized? really? They've had memory controller on the IOD since Zen 2.
These threads are all so sus these days idk why I even read them.
And also like, the real limitation is just having enough pins, they would need a new socket. Elementary
Well, are we really expecting 24C Zen6 to beat 52C Intel Nova Lake-S in MT perf?It's a good question. In fact, another good question would be how is AMD planning on combating the "core wars" advertising? It reminds me of P4 days when the "Mhz wars" raged. It was hard to get people off of the metric that had been ingrained for decades as the metric for performance. AMD finally managed to overcome the problem with model numbers.
Core counts are another problem for AMD IMO. How do you now expect people to understand that 24 AMD cores is better than 52 Intel cores (for the many unfortunate people who aren't part of this forum ).
Well, are we really expecting 24C Zen6 to beat 52C Intel Nova Lake-S in MT perf?
What do you think the total system cost will be for Nova Lake-S 52C vs corresponding AMD TR? Which will be the cheapest solution for comparable MT perf?If someone wants something to beat those 52 cores (lol) they can go AMD all day with TR.
Just to be the undisputed king of cinememe.Im not even sure why Intel would waste any resources on something so retarded.
Yes, there is that.... but then, I think there needs to be more thought at Intel to making money if they want to continue to stay in business.That kind of focus could end up killing some promising projects for enthusiasts, is what I'm worried about.
Z6 is only a newer version. I don't THINK that AMD intends on creating a more "Premium" product with Z6, it is simply the newest itteration of their product lineup. I expect it will START at the top as it always does, then new variants down the chain get released and the last variant is always the integrated graphics super cheap system chip or in this case, Ryzen 10XXX-G.Z6 is a more premium product than Z5 no matter how you cut it, they use a lot of different supply chains and Z6 parts need another packaging step.
Logically Z6 can spare no expense for the pursuit of performance, as Z5 can remain as the more affordable option as they share the same sockets.
If with N2, 50% more cores and the new uncore and packaging they can get enough performance to bump the pricing up a tier, then Z5 can remain with only modest discounts to fit in the cost structure.
It is all up to Intel to disrupt this plan.
AGREE! I think the greater bandwidth and lower latency of the IOD is going to make the most difference. I suspect that Zen 6 will make some tweaks to optimize how well it works with the new IOD as well, but I agree, it is unlikely we are going to see any huge changes in architecture on Zen 6 as the transistor budget isn't going up that much ..... and AMD is already putting 4 more cores on each CCD.... which I think pretty much blows their wad so to speak .The upgraded I/O die has long been rumored to be probably the biggest upgrade with Zen 6. There's no doubt the old I/O die currently in use is holding Zen 5 back. Other than that I think updated decoders would be nice. C&C found that any one thread is still limited to 4 decode and only with SMT can you possibly use them all. Four wide decode has been there since Zen 1. Also a bump in L2 cache size might be nice but I don't expect that just yet. AMD's L3 cache is so much better than Intel's that an L2 miss doesn't hurt as much.
I say their leak is garbage! My speculation is correct and "they can't prove it so they have no argument".You're using arguably-torturous deduction to reason with someone who claims to be looking at a spec sheet. Watching the two of you go back and forth is absurd. Leaks probably don't belong in a speculation thread anyway.
So again either accept what the leakers are saying as canon or simply tell them "you can't prove it so you have no argument" and then speculate with someone else who wants to predict the future.
Good point. It seems like AMD keeps the core architecture the same, but has given up on actually keeping the same LEGO elements in use across all markets. This probably makes a great deal of sense.Zen 4 Ryzen/EYPC/Instinct was the last time AMD stuck with the LEGO® principle. They abandoned it in Zen 5: They have different 8c CCDs for Granite Ridge, Turin, and Strix Halo (Zen 5 thread reference). Of course they are not from-the-ground-up different by any means, but they are not anymore mere different bins at the end of the same conveyor belt.
Perhaps.Well, are we really expecting 24C Zen6 to beat 52C Intel Nova Lake-S in MT perf?
NVL will be much less expensive than TR.What do you think the total system cost will be for Nova Lake-S 52C vs corresponding AMD TR? Which will be the cheapest solution for comparable MT perf?
At least currently, the AMD TR platform and total system cost is quite expensive compared to regular DT.
I believe that you are correct on your first point. NVL is going to be a CB24 monster.Just to be the undisputed king of cinememe.
AMD may only have the option of firing back with dual CCD Zen 6c (16C+16C) for 64 Zen 6c threads or they will need to lower the price of entry for Threadripper.
If you need 52C Nova Lake-S level of MT perf, why would you get corresponding AMD TR if it’s more expensive?NVL will be much less expensive than TR.
For applications that DO justify large core counts, TR will absolutely destroy NVL.
Sonoma Valley is a replacement for Mendocino>>Dali?You're so close, almost there.
1) Use N2 where performance matters most. Server (both types of cores)
Desktop and luggable (where chiplets are used) and probably halo CPU
2) Use N3 where you need volumes and it's more cost sensitive.
Laptop APUs.
3)Use older nodes where cost is the biggest factor
IODs
Still selling zen 5 as low cost desktop and legacy mobile products
There might be some other nodes used. I don't know what happened to Sonoma valley or if there is a replacement for that on the roadmap.
Maybe some iod dies are in (2) as well
IO for both sides has been pretty abysmal forever. IMO the PCI lanes should be doubled. Fast USB gadgets are a thing. Multiple high speed SSDs are a thing, even in a machine with multiple PCIe devices.
Are we calling MLID a source now?MLID expecting high performance (like zen 3 core) from LP cores
Functionally you just need power efficient cores to handle back ground OS tasks & wake up from sleep etc.
Basically extend battery life for low usage scenarios
Because the only applications where that many cores would matter are used by professionals. Professionals won't bat an eye at the higher price of TR as it pays for itself many times over in the increased productivity.If you need 52C Nova Lake-S level of MT perf, why would you get corresponding AMD TR if it’s more expensive?
.Are we calling MLID a source now?