OK, this thread has had enough, this is clearly trolling at this point.
OK, this thread has had enough, this is clearly trolling at this point.Hardly. I suspect that there will be plenty of consumers that buy into the "more cores" marketing that Intel is sure to implement. Very very few people care about gaming on a PC.
Feel free to ridicule me but the core is capable of processing at the rate much higher than what the connection between CCD and IOD allow. Will increasing the avg MemBW by 30% make it suddenlySo the new definition of "well fed" is that main memory has L1 bandwidth?
I would say no. I mean it's better to have that increase than not have it. But the more useful thing would be wider read/write link to memory, as right now single CCD SKU won't be able to even consume this 8000MT/s sensibly. And we don't know what the new IOD will bring. If we go by HALO as the example, it's still not an equivalent of what low core counts Epycs can achieve when it comes to BW available to CCD.just fine even with AVX512.
24 Zen 6 cores is enough to compete. It doesn't need to match it in CB nT, only beat it in 1T. Much like the 7700K didn't need to match the 1800X in nT for it to mop the floor with it in sales. Making a product for the one or two lunatics using a consumer CPU to transcode is an interesting business decision if real.
People don't really need the 4090/5090
I wonder if 144 MB L3 on TSMC N2 passes the 50% Gross Margin test...
Exactly. And as I keep pointing out, and even Intel has noticed, that enthusiasts affect purchasing decisions of people around them.You should refer to latest (Q1) AMD earnings conference call. Higher ASPs especially in desktop were referred to more than once as a contributor to the strong Q1 results.
History shows you can't ignore the enthusiast even though datacenter will get you more profits.X3D has paid for itself more through it's marketing effects than it ever did in per unit margins (data center excluded as I don't know the one and outs of that game well enough).
I doubt that workstation people, in general, care about gaming on PC's (or at all).It just happens that the people who care about performance of PCs coincide with people who care about gaming on PC.
Why is it trolling to point out a fact?OK, this thread has had enough, this is clearly trolling at this point.
Going from 5600 to 8000 I am figuring at 43%. Did I get that right?Feel free to ridicule me but the core is capable of processing at the rate much higher than what the connection between CCD and IOD allow. Will increasing the avg MemBW by 30% make it suddenly
I would say no. I mean it's better to have that increase than not have it. But the more useful thing would be wider read/write link to memory, as right now single CCD SKU won't be able to even consume this 8000MT/s sensibly. And we don't know what the new IOD will bring. If we go by HALO as the example, it's still not an equivalent of what low core counts Epycs can achieve when it comes to BW available to CCD.
At the same time, I really like Zen5 AVX512 implementation, and I hope they won't gimp it for Zen6, as not all algos are memory bound.
DC has the highest margins, not enthusiast parts.Exactly. And as I keep pointing out, and even Intel has noticed, that enthusiasts affect purchasing decisions of people around them.
The companies that ignore the enthusiast segment eventually ends up dying. It's no wonder there are "gaming" versions of every computer parts and even furnitures.
Speaking of margins, the enthusiast parts have the highest margins. Do people really think the office workers care even a bit about the boring boxes under them?
Granted. It is good to be king .Pretty straightforward, having the highest performing parts in a given generation is more than just it's per-unit ASP and margin. It is ALSO a marketing tool. It's existence pays for more marketing reach than most any other marginal increase in marketing expenditures. This is in the managerial accounting textbooks as having a premium offering in a given market segments generates it's own market momentum where the moat is performance/suitability to task and the products are effectively interchangeable.
X3D has paid for itself more through it's marketing effects than it ever did in per unit margins (data center excluded as I don't know the one and outs of that game well enough).
Yea, about that ....History shows you can't ignore the enthusiast even though datacenter will get you more profits.
If you read about history of 3dfx, they got an immense boost because it managed to bring 3D graphics quality not too far from SGI's immensely expensive workstations to the affordable consumer PC.
Let's compare enthusiast focused company versus datacenter only one.
1. Datacenter chips are potentially tens of thousands of dollars. So they don't need to learn about cost efficiency.
2. Datacenter chips are extremely power hungry. So they don't need the latest power management techniques.
3. Datacenter volumes are far less, meaning they need to cater far less in terms of support. Client volumes are massive, meaning you need to focus on every detail, complaints, and whims of the consumer.
Over time, eventually the enthusiast only company looks at datacenter and says "Hey look at the massive revenue potential". And they take their learnings regarding power efficiency, cost efficiency, and great customer support and absolutely dominate the datacenter.
It works perfectly fine on other big/little core CPUs, and it’ll work fine on AMD Zen6 too, unless someone screws up the OS scheduler code.In other words it becomes a balancing act as you have to decide when to handle over, you complicate scheduling and your user who bought 600$ CPU will get choppy experience when trying to run speedometer because you got the scheduling thresholds wrong.
Again, you won’t be getting more performance with TR than 52C NVL unless you go for 64C+ TR. So 16-32C TR will not be sensible to get, unless AMD drops the price significantly on those.Because you want serious performance if you go TR. It's not more complicated with that.
Neither is TR. But we’re talking about what makes most sense to get for that small market segment.I'm not invalidating your user case or your desire for it, but it's not a product with a big market.
So how many do they need? And which of the AMD TR 12-96C SKUs should AMD kill off?Nobody needs 52 cores in a desktop PC.
That’s one single specific use case. There are many others where you don’t need it, especially if we’re talking about ”only” 52C without SMT.They can't get the same performance. If, for instance, your finite element model has so many degrees of freedom that you have good use for fifty-two computing threads, then you also tend to have use for eight DDR5 DRAM channels. (And for memory error detection and correction too.)
Not sure if you’re serious. You’re saying anything above 4C is memory bandwidth bottlenecked on Zen5/Zen6 and NVL-S?If the use case is not data intensive, then a four-core CPU is most often a perfect fit for the use case.
So how many do they need? And which of the AMD TR 12-96C SKUs should AMD kill off?
And note that the user does not care if you label your CPU as DT or HEDT. What they care about is what performance you get for at what price. They’ll buy whatever provides best perf per $, just like everyone else.
You are talking Cinebench only, and that's just boring.Again, you won’t be getting more performance with TR than 52C NVL unless you go for 64C+ TR.
Cinebenching 24/7/365 is not a small market, it is no market at all.But we’re talking about what makes most sense to get for that small market segment.
In all of the real use cases in which you have small datasets, you also don't need "52" (48) threads. (Even in some cases with comparably big datasets, 48 threads get you nowhere where e.g. 16 threads wouldn't get you also.)There are many others where you don’t need [high core counts and decent memory bandwidth combined], especially if we’re talking about ”only” 52C without SMT.
That's news to me lolI’m not about to leak the source (anyone whos anyone knows who posted it) but it’s incorrect that bLLC is only for the dual compute tile SKUs
Raichu is a fairly reliable leaker tbh and he is usually right.Actually, I can’t find ANY mention of bLLC even being on the dual CT version. Yet another reason to not take the professional Chiphell surfer at face value as a primary source
And this is any different between TR and NVL-S or any other CPU how exactly?Performance gains in client, for each additional thread beyond ~32 threads approaches zero.
NoYou are talking Cinebench only
No. Video transcoding and SW compilation just to name some.In all of the real use cases in which you have small datasets, you also don't need "52" (48) threads.
Totally common mom and pop workloads that the average person spends most of their time doing....No
No. Video transcoding and SW compilation just to name some.
Agreed, if the 12C Zen6 X3D part wins the gaming crown, a lot of gamers will get that CPU.Unless the P cores are strong a lot of DIY desktop buyers will buy 11800X3D or whatever AMD name the 12c single CCD X3D part.
Zen6 24C will be SMT so it’s 48T, which is rougly the same number of threads as 52C/T for NVL-S.Also for productivity users the 24C Zen 6 will not be as behind as you think. It will probably lose in CB but in any workloads that don't fully load 52c, which is a lot, you will see better performance with Zen 6
For those that actually need more PCIe lanes or whatever, sure. But for those that just need max MT perf per $, there are huge cost savings by going with regular DT instead of HEDT. For 64C+ there will be no alternative than to go with HEDT, but for 16-32C HEDT will not make sense in most cases unless you have special needs such as more PCIe lanes.If those users really do have need for more than 24c then it will be for a profit motive and TR will be lurking with more PCIe lanes and more mem bandwidth
Never said that. But how many moms and pops will be getting 24C Zen6 or TR for that matter, or run workloads that make full use of them?Totally common mom and pop workloads that the average person spends most of their time doing....
None. Any workload that you use to increase productivity that requires 52c nova lake or TR, i.e.. is very parallel will always take more threads. So TR will win, or epyc. The market for people that need threads but like more than 16 and less than what you can afford is tiny. Either you need threads or you don't.Never said that. But how many moms and pops will be getting 24C Zen6 or TR for that matter, or run workloads that make full use of them?
No. That's not what I said.You’re saying
Mr. Amdahl has a hint for you.SW compilation
Keep in mind that the cores in IOD will not share caches with CCDs. Every time you will put CCD to sleep you have to flush caches (you want to cut power to SRAM too as it always drains power). So when you wake the cores up you have to populate them again, etc. This costs both time and power.
In other words it becomes a balancing act as you have to decide when to handle over, you complicate scheduling and your user who bought 600$ CPU will get choppy experience when trying to run speedometer because you got the scheduling thresholds wrong. Only to save few watts that are drowned out by power innefficiences of the power supply. I mean sure, they might be able to run the workload good enough, but for good enough you could have bought n100
This is why I would dedicate LP cores only to predictable low interactive tasks, ideally background tasks. And ideally give the OS an API that would let software devs mark needed QoS level of the threads their program is using. It is also not to say they will be useless as they can handle background OS stuff giving big cores more time to serve the user.
This could work quite fine with this https://www.guru3d.com/story/windows-11-25h2-introduces-user-interactionaware-cpu-power-management/
But anyway this is more or less my reasoning why
Actually read, not just glance over, what you are responding to. Microsoft is still working on it.¹ They add detection of non-interactive low-energy workload periods. And they seem to add _offlining_ of logical CPUs to power management. (Server operating systems have been supporting logical CPUs going offline and online for some time now. Client operating systems and applications haven't dealt with this yet, and it will be interesting to watch the fallout when it gets introduced to client.)It works perfectly fine on other big/little core CPUs, and it’ll work fine on AMD Zen6 too, unless someone screws up the OS scheduler code.