Question Zen 6 Speculation Thread

[yuri69]

16-channel DDR5-12800 MRDIMM

That's quite a bump from 12ch of DDR5 6400.

Also having EPYC refreshed in just a year.

This is very un-AMD-ish.

 

[coercitiv]

un-AMD-ish

I refrained from posting this morning after reading the news, because it felt like I lacked the proper description for what is happening. Your choice is perfect.

 

[eek2121]

Oh god, we're going to enjoy so many extrapolations from that slide. Jfc.

Not really, if anything, they are derailing hype trains before they hype. Client will see a small IPC bump and a small bump in clocks. It’ll be entertaining to see all the double talking from folks like MLID, etc.

That's quite a bump from 12ch of DDR5 6400.

Also having EPYC refreshed in just a year.

This is very un-AMD-ish.

Competition is nipping at their heals, and by that I don’t mean Intel.

 

[511]

Not really, if anything, they are derailing hype trains before they hype. Client will see a small IPC bump and a small bump in clocks. It’ll be entertaining to see all the double talking from folks like MLID, etc.

Competition is nipping at their heals, and by that I don’t mean Intel.

In DC thay are in CPUs at least .

 

[yuri69]

Not really, if anything, they are derailing hype trains before they hype. Client will see a small IPC bump and a small bump in clocks. It’ll be entertaining to see all the double talking from folks like MLID, etc.

IMO there has been no hype train for the Zen 6 client. It's always been rumored to be a fairly boring incremental Zen 5 with removed ancient IOD baggage.

 

[Io Magnesso]

Even if you say you're catching up, tell me Only NVIDIA's ARM ISA's own design CPU
Qualcomm is also trying to participate, but to be honest, I can only see the ending being crushed by existing players with my current ability... personally

 

[511]

Exactly I see no reason why any hyper scaler wants to buy Qualcomm ARM Chips when they can simply make their own.

 

[StefanR5R]

https://twitter.com/x/status/1933411116396491045

The linked baidu post also shows CCD--IOD arrangements on SP7 (pictured: 2 IODs, 8 32c CCDs) and SP8 (pictured: 2 IODs, 8 12c CCDs).

 

[OneEng2]

Lisa just confirmed Venice is on 2nm at their AI event today.

Woot! Still, this doesn't mean that all flavors of Venice are N2 (although it could mean that).

View attachment 125414

Current reveal from advancing AI

1.27x perf/core * 1.33x more cores = 1.7x perf gain?

4 CCD's per IOD and max 4 IOD -> each CCD is 16 cores.

Sounds about right. The 9965 is already 500 W tho... and even though N2P's power savings is good, 500 W is pushing it.

I heard somewhere that SP7 could support up to 1000W. I fully expect that Venice will draw more power than Zen 5 due to more cores and much more powerful IOD.

Must be, as 256/12 (c Venice CCD) would be 21.3 CCD 🤷🏽‍♂️

See my math above. I am pretty sure we are looking at a 16c CCD.

 

[Kaffeekenan]

Lisa just confirmed Venice is on 2nm at their AI event today.

Uh, you do realize that there was a picture a month ago or so with Lisa and the CEO of TSMC holding up a Wafer with "first 2nm product Venice CCD" writtenon it or something like that. So 2nm for Venice was already confirmed long ago...

 

[511]

It would have been a news if she confirmed it was N2 or N2P.

 

[SteinFG]

The linked baidu post also shows CCD--IOD arrangements on SP7 (pictured: 2 IODs, 8 32c CCDs) and SP8 (pictured: 2 IODs, 8 12c CCDs).

Interesting how they are doing IOD halves for both SP7 and SP8.
For SP7, each IOD-half has 48 gen6 lanes, 4 gen4 lanes, and 8 mem ch.
For SP8, each IOD-half has 64 gen6 lanes, 4 gen4 lanes, and 4 mem ch.

 

[BorisTheBlade82]

Woot! Still, this doesn't mean that all flavors of Venice are N2 (although it could mean that).

4 CCD's per IOD and max 4 IOD -> each CCD is 16 cores.

I heard somewhere that SP7 could support up to 1000W. I fully expect that Venice will draw more power than Zen 5 due to more cores and much more powerful IOD.

See my math above. I am pretty sure we are looking at a 16c CCD.

Then you are pretty much alone with your line of thinking. Every piece of information and every half credible leak points to 32c for Venice Dense and 12c for Venice and Desktop.

 

[StefanR5R]

For what it's worth, AMD's "Advancing AI 2025" slides do not have an end note which would go into details of their 1.7x compute performance statement.

Meanwhile, AMD just switched to giving MI350X and MI355X theoretical peak performance with sparsity (since earlier this week at the ISC 2025 show floor, previously they stated such throughput projections without sparsity). I.e., who is to say that AMD stick to their old ways of stating EPYC performance?

slightly edited for more clarity

 

[511]

For what it's worth, AMD's "Advancing AI 2025" slides do not have an end note which would go into details of their 1.7x compute performance statement.

Meanwhile, AMD just switched from giving MI350X and MI355X theoretical peak performance with sparsity (since earlier this week at the ISC 2025 show floor, earlier they stated such throughput projections without sparsity). I.e., who is to say that AMD stick to their old ways of stating EPYC performance?

Until we get Spec2017 with sparsity support I guess the CPU performance will be done the old ways.

 

[OneEng2]

Interesting how they are doing IOD halves for both SP7 and SP8.
For SP7, each IOD-half has 48 gen6 lanes, 4 gen4 lanes, and 8 mem ch.
For SP8, each IOD-half has 64 gen6 lanes, 4 gen4 lanes, and 4 mem ch.

Then you are pretty much alone with your line of thinking. Every piece of information and every half credible leak points to 32c for Venice Dense and 12c for Venice and Desktop.

A 32c CCD with 2 IOD's = 256 cores sure enough. I just wonder how you are going to feed 256 cores with only 8 channels of DDR5 8000 (assuming that each IOD has 4 channels).

I suppose if Venice Dense doesn't have to move much through memory per thread this would work. I would think that they would need more bandwidth per core than that to be effective.

Of course, the original rumor that each IOD would support 4 CCD's and 4 channels of memory could be incorrect. It could support 4 CCD's and 8 channels of memory. That would make more sense for a 32c CCD.

So what is the speculation on the NON dense Turin then?

 

[inquiss]

A 32c CCD with 2 IOD's = 256 cores sure enough. I just wonder how you are going to feed 256 cores with only 8 channels of DDR5 8000 (assuming that each IOD has 4 channels).

I suppose if Venice Dense doesn't have to move much through memory per thread this would work. I would think that they would need more bandwidth per core than that to be effective.

Of course, the original rumor that each IOD would support 4 CCD's and 4 channels of memory could be incorrect. It could support 4 CCD's and 8 channels of memory. That would make more sense for a 32c CCD.

So what is the speculation on the NON dense Turin then?

You feed it with 12 channel memory

 

[adroc_thurston]

I just wonder how you are going to feed 256 cores with only 8 channels of DDR5 8000

It's 16 channels.

You feed it with 12 channel memory

16.

assuming that each IOD has 4 channels

There are two different sIODs.

 

[inquiss]

It's 16 channels.

16.

There are two different sIODs.

Thanks for the correction.

 

[Saylick]

Uh, you do realize that there was a picture a month ago or so with Lisa and the CEO of TSMC holding up a Wafer with "first 2nm product Venice CCD" writtenon it or something like that. So 2nm for Venice was already confirmed long ago...

lol, I totally forgot about that. Been so busy with work that I haven't been paying much attention to hardware news as much.

 

[OneEng2]

You feed it with 12 channel memory

Lets assume you meant 16 , and we are talking DDR8000.

Current Turin D has 192 cores fed with 12 channels of DDR6000.... or 375MT/core

Venice D would have 256 cores fed with 16 channels of DDR8000 ..... or 500MT/core. So you are correct, this would be an improvement over Turin D and make a great deal of sense.

The current desktop Zen 5 has 16 cores and 2 channels of DDR5600 .... or 933MT/core.

Of course, Turin D 192c is limited to a max of 3.7Ghz while desktop Zen 5 can clock to 5.7Ghz. I think that we have clearly seen that desktop Zen 5 is not currently memory bandwidth bound (unless someone can show me differently).

It's kinda looking to me like Turin D will be quite balanced in its memory bandwidth to core ratio.

There are two different sIODs.

It certainly appears that way. Are you saying that Turin (non D) will use the other one?

 

[MS_AT]

I think that we have clearly seen that desktop Zen 5 is not currently memory bandwidth bound (unless someone can show me differently).

Zen5's AVX512 Teardown + More...

 

[adroc_thurston]

Are you saying that Turin (non D) will use the other one?

did you mean Venice

 

[Tuna-Fish]

Lets assume you meant 16 , and we are talking DDR8000.

... ooor you can use the memory it's actually designed for, and use DDR12800 MCRDIMM.

 

[igor_kavinski]

There are so many designs in flight at Intel now that even if it is officially Zen V: the Return of Conroe I don't see anything dominating like Conroe did for so long.

Zen IV: A New Hope. AMD brings AVX-512 to the masses.

Zen V: The Empire Strikes Back. Or it was supposed to but Darth Gelsinger's lightsaber failed to go off at the wrong moment.

Zen VI: Return of the Jedi. Intel's Death Star goes kaput.