Question Zen 6 Speculation Thread

[Fjodor2001]

So we're talking about X GB/s/core memory bandwidth.

But what X are we expecting to be needed, and for what use case(s), based on what?

And how to put that into context when also considering caches (at different levels) and IMC?

Just as an example: Video transcoding does not require much memory bandwidth, so for that use case is X even close to being a problem on Zen6?

 

[DavidC1]

If it's 8bytes per transfer I see your math. Thanks.

Didn't you say you were an "old timer" or something? This is basics man.

PC platforms have been 64-bit width since SDRAM in the early 90's. Then Pentium 4 introduced Dual Channel with DDR platforms.

64-bit = 8 byte. You need a lesson on that too, how a word is 1 byte and consists of 8 bits? Then the rest is Grade 2 math.

@Fjodor2001 You don't need more than 4 cores in vast majority of use cases either. Yet you still have one. Same with memory bandwidth. There are applications that need more, and this is a general purpose CPU, meaning you don't know what the users will need it for. It needs to be fast in all.

 

[RnR_au]

1.6TB of membw is 5090's levels of membw. Its 4 times larger than an Apple M2 Ultra and nearly 3 times faster than a Apple M4 Max (GPU access speeds). Depending on costs and available form factors, I have a feeling that many 'local AI' enthusiasts will be adopting this EPYC platform.

 

[OneEng2]

I can't find anyplace that says venice MIGHT have 92 cores. Only 96 and 128.
I also don't think the 96 core would be in compition for Panther lake, only the 128 core varieties, and I think Zen 6 would beat them. We will see.

My mistake.

I tend to agree with your assessment, but I am still wondering how much performance the basic ARL core has that is simply being held hostage by the obscene latency. Perhaps IF that can be cleaned up it would breath new life into the design and we could have another Core moment at Intel?

Possibly not, but still, not out of the realm of possibility.

You either do not understand what we are talking about or trolling. To validate your claim you would need to compare 9950X against a 16C Epyc F chip (F to minimize clock difference) and then compare their performance in those benchmarks. Places where Epyc will win are memory bound. Assuming the software is CCD aware and things like that.

The fact that 9950x won in the comparisons you posted does not mean it is not memory bandwidth limited. It means that either these workloads are not bound by memory bandwidth or from chips that participated in the test it had the best bandwidth to compute ratio.

Why is it that so many people are calling me a troll when I simply disagree with their POV?

I assume that since your opinion on this is so strong, that you have SOME shred of proof (other than Y cruncher which likely runs in cache and never touches main memory AT ALL) that Zen 5 is currently bandwidth limited in some case. If so, than please post it.

FYI, you don't need an EPYC benchmark vs desktop benchmark (and it likely would be contaminated with many other factors anyway). You simply need a benchmark that shows faster memory having significant influence on some Zen 5 benchmark.

Didn't you say you were an "old timer" or something? This is basics man.

PC platforms have been 64-bit width since SDRAM in the early 90's. Then Pentium 4 introduced Dual Channel with DDR platforms.

64-bit = 8 byte. You need a lesson on that too, how a word is 1 byte and consists of 8 bits? Then the rest is Grade 2 math.

Grow up..... seriously. If you don't have anything constructive to say, I would prefer you simply ignore my posts.

 

[adroc_thurston]

I have a feeling that many 'local AI' enthusiasts will be adopting this EPYC platform

That's far beyond their cost range.

 

[OneEng2]

1.6TB of membw is 5090's levels of membw. Its 4 times larger than an Apple M2 Ultra and nearly 3 times faster than a Apple M4 Max (GPU access speeds). Depending on costs and available form factors, I have a feeling that many 'local AI' enthusiasts will be adopting this EPYC platform.

Does anyone know what memory Intel is planning on using in DC for their next gen processors? .... and how many channels?

 

[igor_kavinski]

(other than Y cruncher which likely runs in cache and never touches main memory AT ALL)

y-cruncher does run in RAM. For calculating 2.5 billion digits of pi, it needs about 16GB RAM and it's actually a really good way to test if your RAM overclock is fine or even if your stock settings are stable. Errors out immediately in case of instability, even when everything else seems to be running fine so prevents you from using RAM settings that may silently corrupt data.

 

[DrMrLordX]

Yeah they make money at ARM's expense.

Yeah, it's gonna be "pay real licensing costs or shop our merchant Si" kinda deal.

That's what the ARM intentions / agenda seems to be. I wonder if ARM can pull it off.

ARM had a setback suing QCOM. Different basis of lawsuit vs. ARM's issues with Amazon. Only the same in that ARM wants a lot more money from licensing than before.

If ARM raises the price too much on Neoverse, they'll kill whatever business case Amazon et al had for licensing the Neoverse platform (versus buying EPYC). Of course with ARM buying out Ampere and with Qualcomm getting back into the ARM server game, that makes Neoverse potentially even less attractive for in-house development.

y-cruncher does run in RAM.

Not just RAM, it'll run in virtual memory beyond a certain point, turning it into a storage benchmark more than anything else.

 

[Darkmont]

y-cruncher does run in RAM. For calculating 2.5 billion digits of pi, it needs about 16GB RAM and it's actually a really good way to test if your RAM overclock is fine or even if your stock settings are stable. Errors out immediately in case of instability, even when everything else seems to be running fine so prevents you from using RAM settings that may silently corrupt data.

The fact that he thought Y CRUNCHER ran in cache immediately makes me think he’s too ignorant to be trolling

 

[dr1337]

Just as an example: Video transcoding does not require much memory bandwidth, so for that use case is X even close to being a problem on Zen6?

I have looked at dozens of benchmarks on a certain competitor platform (THAT OBJECTIVELY HAS MORE MT PERF) that supports both DDR4 and DDR5, and have not ever found a single real world benchmark that has massive difference. Ergo AMD (or any other vendor) with a particular memory BW/latency advantage would be immediately apparent, but its not.

I am very worried that here in 2025 benchmarks aren't useful like they were half a decade ago due to to a multiple of biases. So people that claim bandwidth matter must either be lying or not telling the full truth about their technical needs.

 

[igor_kavinski]

The fact that he thought Y CRUNCHER ran in cache immediately makes me think he’s too ignorant to be trolling

TBH, I would've thought that too until I used it. Instantly became a fan. It's amazing for the price of $0.

 

[igor_kavinski]

Not just RAM, it'll run in virtual memory beyond a certain point, turning it into a storage benchmark more than anything else.

Yeah, the author warns not to run it on SSD unless you like seeing SSDs die prematurely.

 

[igor_kavinski]

I have looked at dozens of benchmarks on a certain competitor platform (THAT OBJECTIVELY HAS MORE MT PERF) that supports both DDR4 and DDR5, and have not ever found a single real world benchmark that has massive difference. Ergo AMD (or any other vendor) with a particular memory BW/latency advantage would be immediately apparent, but its not.

Weird performance difference between Ryzen 5900X and 7950X · Issue #4716 · ggml-org/llama.cpp

Did some benchmarking tonight and have a Ryzen 5900X that beats a 7950X for some reason at 3.58 vs 3.37 t/s on Mixtral Q8_0. Similar results for other quants and with Phi-2. This shouldn't be the c...

github.com

DDR5 vs. DDR4 in the Latest PC Games

As next-gen CPUs quickly approach, we've updated all our CPU benchmark data and have retested some Intel CPUs to highlight DDR5's impact on modern PC gaming performance....

www.techspot.com

Depends on your definition of real world. Excel and data science workloads should also benefit greatly from increased bandwidth.

 

[MS_AT]

Why is it that so many people are calling me a troll when I simply disagree with their POV?

That is a good question, isn't it?

I assume that since your opinion on this is so strong, that you have SOME shred of proof (other than Y cruncher which likely runs in cache and never touches main memory AT ALL) that Zen 5 is currently bandwidth limited in some case. If so, than please post it.

I posted what I believe is an article that very well explains the problem, listing also in which applications it becomes noticeable. I posted an article authored by someone who is recognized as knowledgable person in the field. Yet your response suggest you have not read it, so I don't see a point to continue.

FYI, you don't need an EPYC benchmark vs desktop benchmark (and it likely would be contaminated with many other factors anyway). You simply need a benchmark that shows faster memory having significant influence on some Zen 5 benchmark.

Yes, indeed you can do that, but using epyc chip not only gives you more memory channels but also twice as wide CCD to IOD link. Together these two facts would make the bandwidth dependency more visible when you compare the two.

 

[OneEng2]

y-cruncher does run in RAM. For calculating 2.5 billion digits of pi, it needs about 16GB RAM and it's actually a really good way to test if your RAM overclock is fine or even if your stock settings are stable. Errors out immediately in case of instability, even when everything else seems to be running fine so prevents you from using RAM settings that may silently corrupt data.

I see. Strange way to test bandwidth then.

The fact that he thought Y CRUNCHER ran in cache immediately makes me think he’s too ignorant to be trolling

It's easy to never be wrong when you never say anything yourself worth while.

So how about addressing the actual question at hand since you are such a genius?

Is Zen 5 in any configuration on any real world application memory constrained?

I have looked at dozens of benchmarks on a certain competitor platform (THAT OBJECTIVELY HAS MORE MT PERF) that supports both DDR4 and DDR5, and have not ever found a single real world benchmark that has massive difference. Ergo AMD (or any other vendor) with a particular memory BW/latency advantag!e would be immediately apparent, but its not.

I am very worried that here in 2025 benchmarks aren't useful like they were half a decade ago due to to a multiple of biases. So people that claim bandwidth matter must either be lying or not telling the full truth about their technical needs.

If that is the case, why is AMD going out of their way to so drastically increase bandwidth per core for Venice?

Granted, my request for some real world example has so far been answered only by y cruncher... Which is laughable in the extreme if on is asking about real DC applications.

Still, it seems like there must be a good example out there, just a real lack of dedication here to find it and instead start calling names.

FWIW, I contribute to this forum because it seemed to have a good deal of mature discussion. Less so lately though. Starting to seem more like a bunch of middle school kids at recess

Weird performance difference between Ryzen 5900X and 7950X · Issue #4716 · ggml-org/llama.cpp

Did some benchmarking tonight and have a Ryzen 5900X that beats a 7950X for some reason at 3.58 vs 3.37 t/s on Mixtral Q8_0. Similar results for other quants and with Phi-2. This shouldn't be the c...

github.com

DDR5 vs. DDR4 in the Latest PC Games

As next-gen CPUs quickly approach, we've updated all our CPU benchmark data and have retested some Intel CPUs to highlight DDR5's impact on modern PC gaming performance....

www.techspot.com

Depends on your definition of real world. Excel and data science workloads should also benefit greatly from increased bandwidth.

I thought it was universally agreed that gaming was much more sensitive to latency than bandwidth.

Comparing two different memory controllers introduces too many variables into the comparison IMO.
.

 

[igor_kavinski]

I thought it was universally agreed that gaming was much more sensitive to latency than bandwidth..

Depends on the game engine. Also, Alder/Raptor Lake cores are serious data crunchers and they are starved for bandwidth. You can see it in the video linked in the comments section of the Techspot article.



Only one game engine in their test suite seems to prefer DDR4-4000. Everything else saw an improvement with DDR5-7200.

DDR4 vs. DDR5 on Intel Core i9-12900K Alder Lake Review

The Intel Alder Lake platform has support for both DDR5 and DDR4 memory. We ran 38 application benchmarks and 10 games at multiple DDR4 configurations to learn what performance to expect when using DDR4 vs. DDR5 on 12th Gen, and whether there's a point at which DDR4 performance can beat the much...

www.techpowerup.com

TPU's testing is older so we could say that DDR4-3600 is roughly equal to DDR5-6000.

The individual game results show how different each game engine is in its memory access patterns so there's no real clear winner but I bet DDR5-7200 would've come out as superior in most of these games.

 

[StefanR5R]

why is AMD going out of their way to so drastically increase bandwidth per core for Venice?

I wouldn't call it a drastic increase in memory bandwidth per core. a) Not all deployments will use MR-DIMMs, and who knows how many deployments will be able to actually implement the maximum of 16 channels/socket, b) both core count and perf/core will increase, c) CPU-to-GPU throughput IOW PCIe (edit: PCIe/ Infinity Fabric/ UALink) throughput will increase by an even greater factor than CPU-to-main memory throughput. Top of the line NICs will also advance from 400G to 800G; at the same time, rack-level connectivity is now playing a decisive role not just for Nvidia but also for AMD, they need to back this with memory bandwidth.

Also, both Intel and AMD already have very high bandwidth/core products in their portfolios. IOW, Venice doesn't actually stand out in this regard. Intel was first both with HBM-enabled Xeon and then with MCR-DIMM support. AMD made MI300C for Azure. Before that, folks who needed memory bandwidth simply went with medium-to-low core counts per socket but multi-socket or even multi-node setups.

Granted, my request for some real world example has so far been answered only by y cruncher... Which is laughable in the extreme if on is asking about real DC applications.

Still, it seems like there must be a good example out there, just a real lack of dedication here to find it and instead start calling names.

Various HPC applications are well known to crave memory bandwidth. Computational fluid dynamics, seismic simulations, that kind of stuff. Finite element analysis if model size is non-trivial. Any post processing after such simulations, because once the solver is done, you are left with mountains and mountains of results that you need to convert in various ways. Some stages in electronic design automation are memory bandwidth bound too AFAIK. And the not-so-new kid on the block: What is now called AI.

 

[Darkmont]

It's easy to never be wrong when you never say anything yourself worth while.

So how about addressing the actual question at hand since you are such a genius?

Is Zen 5 in any configuration on any real world application memory constrained?

1. Life Science and Biological Simulations such as NEMO (Ocean Modeling), CFD, Machine Learning, Graph Analytics, Video and Image transcoding and processing, In memory databases like SAP HANA, Data Analytics like Apache Spark, the list Stefan also provided.

2. The only worth while thing you contribute to this forum is making other people spend less time on the computer so they don't have to suffer through the CBT of reading your slop. Reading your messages is like visiting a mini Gitmo. Can anyone on this forum confidently say they've ever been made smarter by something you said except researching an answer to correct you?

 

[soresu]

The only worth while thing you contribute to this forum is making other people spend less time on the computer so they don't have to suffer through the CBT of reading your slop

Careful now, I'm pretty sure that personal attacks are a big nono in this forum.

 

[DavidC1]

Careful now, I'm pretty sure that personal attacks are a big nono in this forum.

Yea... and I know what that kind of running a place is called. But I won't say it.

 

[Fjodor2001]

Life Science and Biological Simulations such as NEMO (Ocean Modeling), CFD, Machine Learning, Graph Analytics, Video and Image transcoding and processing, In memory databases like SAP HANA, Data Analytics like Apache Spark, the list Stefan also provided.

Do you have any benchmarks showing how much impact the memory bandwidth has for such use cases?

 

[adroc_thurston]

Do you have any benchmarks showing how much impact the memory bandwidth has for such use cases?

Yes and you can also spin a MI300C instance on Azure for that.

 

[CouncilorIrissa]

Do you have any benchmarks showing how much impact the memory bandwidth has for such use cases?

Enough of an impact to make the STXH that runs at 5.1 GHz (in 1t obviously, much slower in nT) at much more conservative power (apparently it does not go above 42W for CPU-only workloads) settings pull ahead of a juiced 9950X in something like a Photo Filter/Horizon Detection subtests of gb6 (the full description of the test available here at page 27) nT suite.

 

[Darkmont]

https://upcommons.upc.edu/bitstream/handle/2117/134613/TMR1de1.pdf
Sure Fjodor, check pages 51-55. The entire thesis is worth reading if you've got the time.
https://people.kth.se/~mebr/assets/files/PDP2021_Application Characterization for Near Memory.pdf A shorter paper with results on figure 3. As an aside, the addition of channels is as much a capacity play as it is a bandwidth one to not be bound to the tortoise release cadence of denser DDR5 from DRAM co.

 

[Io Magnesso]

The wider the bandwidth, the better, as the IPC will be improved accordingly.
Rather than having a problem with the ZEN5 bandwidth, the AM5/IO Die, which is a consumer environment, feels like a bottleneck.
Spec2017 of EPYC9015 has a much better result than the 9950X, which is supposed to have more cores. (Memory speed is 4800)