Question Zen 6 Speculation Thread

[Joe NYC]

There's panel-level fanouts but they're 2028+ and not for this console gen.

Combined size of the chipet AMD is dealing with is not overwhelmingly large, within 400 mm2, so still a good number can fit on 300mm wafer.

That's about as encroaching as soviets in Africa doing the cold war. Gibs stop, and so will the DC MSS creep.

Bergamo is only the first attempt. Turin Dense and Venice Dense should be able to compete better.

But I will convinced only when the hyperscalers substantially scale down their in house Arm ambitions.

Super8 already has extensive influence on AMD's big socket roadmap. They do not need to do anything more.

One of the stated reasons for the hyperscalers in-house design (with Arm) is greater customizability to their own needs.

Which seems like a recipe for AMD semi-custom.

Are they suddenly going to be fine with one size fits all?

 

[Joe NYC]

Is it a semi-custom to AMD hyperscaler…
Certainly, there was also a MI300C, a customized MI300 product for Azure.

I think it was just an existing design in search of customer, and AMD just calls it "semicustom" when a customer finally signed up.

 

[Io Magnesso]

Combined size of the chipet AMD is dealing with is not overwhelmingly large, within 400 mm2, so still a good number can fit on 300mm wafer.



Bergamo is only the first attempt. Turin Dense and Venice Dense are better to compete.

But I will convinced only when the hyperscalers substantially scale down their in house Arm ambitions.



One of the stated reasons for the hyperscalers in-house design (with Arm) is greater customizability to their own needs.

Which seems like a recipe for AMD semi-custom.

Are they suddenly going to be fine with one size fits all?

Hyperscalers seem to be fine as long as they are cheap and customized to suit their needs.
If Intel or AMD customized based on existing products, if they match their demands X86 is fine too.
I'm not strong at the moment, but if a better IP comes out, I can choose RISC-V.

 

[adroc_thurston]

Combined size of the chipet AMD is dealing with is not overwhelmingly large, within 400 mm2, so still a good number can fit on 300mm wafer.

You do understand that in WLP you're limited by the number of substrates per wafer, not the tiles on top of 'em.

Bergamo is only the first attempt. Turin Dense and Venice Dense should be able to compete better.

That's not what I'm talking about.

One of the stated reasons for the hyperscalers in-house design (with Arm) is greater customizability to their own needs.

No it's cheap IP.
They customize nothing.
Microsoft/GOOG stuff is outright Neoverse CSS on a stick.

Which seems like a recipe for AMD semi-custom.

Semi-custom is consoles.

Hyperscalers seem to be fine as long as they are cheap and customized to suit their needs.

They do not customize anything.

 

[Io Magnesso]

You know that besides raw there's also parametric yield ?

It's no custom at all.

Is it Parametric Yield? Yes, of course I know
That's why chiplets have a meaning.

 

[Joe NYC]

You do understand that in WLP you're limited by the number of substrates per wafer, not the tiles on top of 'em.

It's not like they would be wasting a lot of space between the area of the wafer and area of the sum of the tiles.

That's not what I'm talking about.

No it's cheap IP.
They customize nothing.
Microsoft/GOOG stuff is outright Neoverse CSS on a stick.

What will, then, change the direction of MS movement, which is still in favor of Arm?

Arm substantially increasing the licensing fees could be one variable.

But before that happens, as long as the hypers are continuing their in-house Arm effort, MS is going to inch in Arm direction.

It could change if AMD could offer something that changes the value proposition in another way, through offering some customization, perhaps

Semi-custom is consoles.

Also Tesla infotainment is counted there, AFAIK.

But this is so mainly because the datacenter side has not managed any semicustom wins.

 

[adroc_thurston]

It's not like they would be wasting a lot of space between the area of the wafer and area of the sum of the tiles.

Yeah you do.

But before that happens, as long as the hypers are continuing their in-house Arm effort

It's not in-house, they use ARM's IP.
It's viable as long as it's cheap, but that's not forever.

Also Tesla infotainment is counted there, AFAIK.

Pocket change.

 

[maddie]

Is it Parametric Yield? Yes, of course I know
That's why chiplets have a meaning.

True.

Some seem to have forgotten that smaller chiplets allow higher performing bins than available to larger dies. The chance of the whole die being limited by a poorly performing section increases greatly with die area.

I suggest they re-read the papers that led to the original Ryzen processors.

 

[soresu]

That's why chiplets have a meaning.

Also design costs.

Designing beeeg dies has beeeg costs to go with it - AI/ML design tools may be helping to take some of that load off as it gets more and more complex, but it's still anything but trivial to design a 600mm² die vs a 100-150mm² one.

Chiplets allow for a very versatile potential SKU stack with minimised design costs.

 

[adroc_thurston]

but it's still anything but trivial to design a 600mm² die vs a 100-150mm² one.

Not really?
A 150mm^2 phone SoC is eons more complex than a 600mm^2 GPU.

 

[poke01]

Not really?
A 150mm^2 phone SoC is eons more complex than a 600mm^2 GPU.

Is it cause different IP have meld together well?

 

[soresu]

Not really?
A 150mm^2 phone SoC is eons more complex than a 600mm^2 GPU.

What on earth gave you the impression I was talking about smartphone SoCs? 😵‍💫

I was actually talking about Epyc specifically.

 

[adroc_thurston]

Is it cause different IP have meld together well?

Yeah.

What on earth gave you the impression I was talking about smartphone SoCs?

You generalized.

I was actually talking about Epyc specifically

Server SOCs are also IP soups where platform complexity is the main validation factor and not the die area.

 

[soresu]

You generalized.

I specifically mentioned a versatile SKU stack based multiples of a small die chiplet, which describes Epyc perfectly.

 

[adroc_thurston]

I specifically mentioned a versatile SKU stack based multiples of a small die chiplet

I have bad news, Venice has more discrete tapeouts than ever, all to address specific market niches.

 

[soresu]

Is it cause different IP have meld together well?

Well yes and no.

Yes in theory, but no in the case of ARM where the synthesizable IP probably has the greater part of the IP interoperability prebaked in as long as you are using just their IP, combined with the fact that ARM works with TSMC and Samsung to synergize on process.

(the uncore interconnect is actually marked on their IP roadmap too)

If you are using a bunch of custom in house (a la Google TPU) or other 3rd party silicon with it then good luck to you sir 😵💀

 

[soresu]

I have bad news, Venice has more discrete tapeouts than ever, all to address specific market niches.

Yes, but that does not detract from the fact that chiplets offer greater versatility within those discrete SKU groups than just one whacking huge core/cache die with bad yields determining core count binning.

You still get the option of die binning with chiplets, but on top of chiplet scaling up to the limit of package size, number of IOD links and socket thermal dissipation.

 

[adroc_thurston]

the fact that chiplets offer greater versatility within those discrete SKU groups than just one whacking huge core/cache die with bad yields determining core count binning

There's no difference, AMD bins them just as much.
That's also the reason Intel always had 3 dies per Xeon generation.

Chiplets are for winning more.
They let you spam moar Si.

 

[Det0x]

Remember to take your salts and everything

Do we have any confirmation that its the Zen4 team thats responsible for Zen6 ?

My take, Zen6 will win everything thats not embarrassing parallel and Nova Lake will comsume 350-400w when tuned to actually have decent cinebench performance
Very few apps/games/benchmarks can take full advantage of the 48 threads/cores is also a drawback, espescally if the rumored 8P16E + 8P16E + 4LPE(SOC) on two different compute dies are true, making the windows scheduling doomed to fail

 

[adroc_thurston]

Do we have any confirmation that its the Zen4 team that responsible for Zen6

Idk but you can always check Troester LinkedIn.

 

[adroc_thurston]

The answer is maybe.

 

[CouncilorIrissa]

View attachment 125997
The answer is maybe.

Troester, huh?
edit: nvm, just saw the post above

 

[Kepler_L2]

Remember to take your salts and everything

Do we have any confirmation that its the Zen4 team thats responsible for Zen6 ?

My take, Zen6 will win everything thats not embarrassing parallel and Nova Lake will comsume 350-400w when tuned to actually have decent cinebench performance
Very few apps/games/benchmarks can take full advantage of the 48 threads/cores is also a drawback, espescally if the rumored 8P16E + 8P16E + 4LPE(SOC) on two different compute dies are true, making the windows scheduling doomed to fail

AMD hasn't hit a frequency target in like 5 years so Zen6 perf is still very TBD.

 

[adroc_thurston]

AMD hasn't hit a frequency target in like 5 years

They do have extremely ambitious ones doe.

 

[Fjodor2001]

Very few apps/games/benchmarks can take full advantage of the 48 threads/cores is also a drawback

A drawback for which CPU? Both Zen6 and NVL-S will have 48T on DT.

(If you exclude the LPE cores, which both will have.)