Question Zen 6 Speculation Thread

[Thunder 57]

Compared to the 12-core X3D?

Yes. It will depend on models and price though.

 

[Io Magnesso]

Yes. It will depend on models and price though.

There's certainly no way to avoid a price increase I accept
But personally, I'm happy that single CCD improves multi-threading performance.
No matter how much you try to improve the IOD with Zen6, you have to cross the IOD with 2CCD.
It would be nice if AMD could prepare the X3D version for the 8-core model of the lower model.

 

[Fjodor2001]

I just can't imagine anyone but the cinebench graphers buying a 48 core CPU on 2 channel memory in 2026/7.

Same for AMD then, since they'll also have a 48T CPU on 2 channel memory in 2026/7.

If anything Intel should likely have the advantage of supporting faster DDR5 speeds. But this is only relevant for those MT use cases where memory speed will affect performance to a large degree, which is only a subset of all MT use cases.

 

[Fjodor2001]

That says nothing about Novalake being better than Zen 6.

Because you could have a 50W 16+32 chip just by clocking it low enough. But your performance will suck.

It says that the MT performance will be better given a certain power consumption restriction. And I'm talking about the range of ~150W TDP which is expected for NVL-S.

Basically you get more perf/watt if you stay in the lower frequency range where perf/watt is better. I.e. better to have many cores operating in the lower frequency range, than fewer cores operating in the highest frequency range. This because when you push the cores towards max frequency, you get very little extra perf but the power consumption increases a lot.

 

[Abwx]

We’re talking about different things.

I was talking about perf/watt when not pushing the cores to max perf (or max TDP).

But that s exactly perf/watt, they encode a file using Handbrake, there s nothing that is pushed here, the 285K consume 35% more, 222W vs 159W for the first pass that is lightly threaded and 263W vs 196W for the second pass that is heavily mutlithreaded,

The 9950X has 42% better perf/watt since it s actually 2% faster in this task, the review i linked used an older Handbrake version where it s 5-6% slower but it has been updated by Computerbase in their recent CPU round up.

 

[whoshere]

Will desktop Zen 6's IO die be reworked or it will continue to gulp 20-40W doing nothing?

 

[Fjodor2001]

This has little to do with cores lol and everything to do with AMD paying a constant 20-25W penalty due to an antiquated IOD (which they will no longer be paying with Zen 6: looking at you, Strix Halo).

That's part of the explanation, but not all of it. It's about the efficiency of the cores too.

Also, Zen5 IOD does not consume 20-25W more than corresponding dies for Intel. It's not like the ones Intel uses do not consume any power at all.

 

[Fjodor2001]

But that s exactly perf/watt, they encode a file using Handbrake, there s nothing that is pushed here, the 285K consume 35% more, 222W vs 159W for the first pass that is lightly threaded and 263W vs 196W for the second pass that is heavily mutlithreaded,

The 9950X has 42% better perf/watt since it s actually 2% faster in this task, the review i linked used an older Handbrake version where it s 5-6% slower but it has been updated by Computerbase in their recent CPU round up.

I was talking about perf/watt when you limit the power consumption, so it does not run at stock TDP.

Check the TDP scaling graph I linked to before.

 

[Timorous]

Yes. It will depend on models and price though.

They won't make an 8 core for a while so it will be pay up for the 12c or go without.

 

[whoshere]

A world of difference. Almost exactly 25W more doing absolutely nothing.

 

[Io Magnesso]

That's part of the explanation, but not all of it. It's about the efficiency of the cores too.

Also, Zen5 IOD does not consume 20-25W more than corresponding dies for Intel. It's not like the ones Intel uses do not consume any power at all.

Certainly, there was a lot of power consumption at idle, right?

 

[Fjodor2001]

Certainly, there was a lot of power consumption at idle, right?

The problem with that graph is that it's total system power consumption at idle, so it's hard to know what parts of the system consume what part of the power. GPU, IOD, memory, SSD, CPU cores, mother board, etc. So you cannot tell how much the IOD consumes based on that graph.

That said, the Zen5 IOD is bad w.r.t. power consumption, no doubt. The question is just how bad, or how many watts more it consumes compared to what Intel uses.

An open question is also what we can expect from the IOD for Zen6. It'll be on a newer node, so it'll consume less due to that, all else equal. But do we know if it'll catch up completely, and be on par with what Intel will be using for NVL-S?

 

[Io Magnesso]

The problem with that graph is that it's total system power consumption at idle, so it's hard to know what parts of the system consume what part of the power. GPU, IOD, memory, SSD, CPU cores, mother board, etc.

I know that
However, I think I've seen a comparison of the power consumption when idle with the CPU alone somewhere.
I think Intel was pretty low

 

[whoshere]

Spoiler: CPU die alone:

eTeknix clearly made a mistake:

On average 9W for the 285K vs over 40W for Zen 5 (9950X).

 

[igor_kavinski]

day 9592 of anandtech posters pretending there's a mythical workload that scales infinitely with cores, while not giving a crap about membw AND not needing to be correct (aka requiring ECC from workstation/HEDT boards).

Ummm...do greater number of threads not exist? More cores to handle OS/background threads means less time wasted in context switching. Overall system responsiveness is improved. More cores may not scale all that well but they are not going to be completely useless. One thing that is not measured/benchmarked very well is real user workloads where they may have multiple applications open at the same time and switching between them frequently. Not all threads are I/O bound so the membw may not be an issue in the majority of the cases. I don't see why increasing cores should be considered a problem. If you build them, use cases will follow soon enough.

 

[Io Magnesso]

Ummm...do greater number of threads not exist? More cores to handle OS/background threads means less time wasted in context switching. Overall system responsiveness is improved. More cores may not scale all that well but they are not going to be completely useless. One thing that is not measured/benchmarked very well is real user workloads where they may have multiple applications open at the same time and switching between them frequently. Not all threads are I/O bound so the membw may not be an issue in the majority of the cases. I don't see why increasing cores should be considered a problem. If you build them, use cases will follow soon enough.

I want a multi-way SMT...

 

[soresu]

I want a multi-way SMT...

If the decoder gets split again in a future µArch that doesn't seem like such a stretch.

IIRC the new 2 way decoder (2x 4 wide actual vs 1x 8 wide expected) in Zen5 actually increased SMT performance significantly more than single threaded performance.

 

[jpiniero]

I want a multi-way SMT...

SMT4!!!

 

[igor_kavinski]

I want a multi-way SMT...

@Cheesecake16

Tricky question (seems to me): Does SMT4 and SMT8 benefit CPUs with more pipeline stages and higher speeds? Is SMT missing in "-mont architecture" CPUs because they are low clocked so SMT throughput wouldn't be high enough to warrant wasting transistors on it?

 

[soresu]

@Cheesecake16

Tricky question (seems to me): Does SMT4 and SMT8 benefit CPUs with more pipeline stages and higher speeds? Is SMT missing in "-mont architecture" CPUs because they are low clocked so SMT throughput wouldn't be high enough to warrant wasting transistors on it?

Given *mont loses efficiency to *cove cores it seems like perf/area optimisation is their main target, so better to just try and make the cores smaller and have moar going by the core spam strategy Nova Lake is rumored to employ.

 

[igor_kavinski]

Given *mont loses efficiency to *cove cores it seems like perf/area optimisation is their main target, so better to just try and make the cores smaller and have moar going by the core cpam Nova Lake is rumored to have.

Yeah but doesn't it make you wonder? If only 5% more transistor cost could double the resource utilization of the mont cores, why not do that???

 

[CouncilorIrissa]

Ummm...do greater number of threads not exist? More cores to handle OS/background threads means less time wasted in context switching. Overall system responsiveness is improved. More cores may not scale all that well but they are not going to be completely useless. One thing that is not measured/benchmarked very well is real user workloads where they may have multiple applications open at the same time and switching between them frequently. Not all threads are I/O bound so the membw may not be an issue in the majority of the cases. I don't see why increasing cores should be considered a problem. If you build them, use cases will follow soon enough.

It's an irrrelevant market. Very few people want/need more cores or threads. Intel wouldn't be forced to drop 265KF to $230 to sell a meaningful number of them, whereas AMD is laughing all the way to the bank selling an 8-core chip for $470, despite the 265KF being a better choice in literally every single way except that one use case the majority of users care about.

And adding more cores to your core interconnect, be it ring or something else, isn't free.

 

[Io Magnesso]

Given *mont loses efficiency to *cove cores it seems like perf/area optimisation is their main target, so better to just try and make the cores smaller and have moar going by the core spam strategy Nova Lake is rumored to employ.

I don't think the mont architecture is inefficient…
Perhaps, although I'm not using it now, Gracemont/Crestmont/Skymont has SMT, maybe there's a preset.

 

[Io Magnesso]

It's an irrrelevant market. Very few people want/need more cores or threads. Intel wouldn't be forced to drop 265KF to $230 to sell a meaningful number of them, whereas AMD is laughing all the way to the bank selling an 8-core chip for $470, despite the 265KF being a better choice in literally every single way except that one use case the majority of users care about.

And adding more cores to your core interconnect, be it ring or something else, isn't free.

Sure, many users don't need a lot of cores.
However, it is likely that the number of cores used by the general public will steadily increase
It's slow, but has progressed to 4 cores/6 cores/8 cores.

 

[soresu]

I don't think the mont architecture is inefficient…

I didn't say inefficient, I said less efficient than *cove cores of the same generation for IPC.

Their primary design target is perf/area to maximise core counts (like Zen #c), not absolute perf like *cove.