Question Zen 6 Speculation Thread

[Kepler_L2]

Pointless for me to argue. Believe what you will.

Anyone taking bets on Zen 6 desktop max clocks?

Using a bit of history and math:

Zen4 missed freq target by 5% (5.7 vs 6)
RDNA3 missed freq target by 21% (2.5 vs 3.15)
Zen5 missed freq target by 5% (5.7 vs 6)
RDNA4 missed freq target by 14% (2.97 vs 3.46)

MLID is implying their target is 7 GHz, so:

If we take their average CPU freq target miss in the last 2 generations (5%), they would hit 6.65 GHz
If we take both their CPU and GPU average freq target miss in the last 2 generations (11.25%), they would hit 6.21 GHz

 

[511]

Using a bit of history and math:

Zen4 missed freq target by 5% (5.7 vs 6)
RDNA3 missed freq target by 21% (2.5 vs 3.15)
Zen5 missed freq target by 5% (5.7 vs 6)
RDNA4 missed freq target by 14% (2.97 vs 3.46)

MLID is implying their target is 7 GHz, so:

You said all the right things but you put MLID here I would unbelive the 7Ghz 😛.
Anyway a realistic target would be 6.2-6.4 GHz imo.

 

[Tuna-Fish]

And just to expand a little, Zen 6 is more than a year from launch, literally no-one anywhere knows what the clocks will be. Final clocks are only set based on statistics after significant amount of data from real, mass manufactured chips is available, often just weeks before launch.

All anyone (including inside AMD) has right now is the clock target, and possibly just a handful of data points from early samples. People keep getting surprised by clocks on modern processes (and usually in the downwards direction). Any leaks from people who claim to know anything more than the target are made up.

 

[OneEng2]

6.0 GHz

I don't think AMD will risk going above that. They are usually conservative with their clocks unless Intel is clocking really high.

I think that if Zen 6 comes out before Nova Lake, it will be 6.0Ghz .... maybe 6.2Ghz. They may have the headroom, but they will not want to use it. Better to yield higher (and cheaper) than to use headroom you didn't need to best the competition.

Zen 6 appears to be to Zen 5, what Zen 4 was to Zen 3, only with even more cores. So unless Intel has another Alder Lake moment, AMD is safe.

Maybe.

That seems absurdly high imo. I think Zen 6 can improve ST performance by 20%, roughly half from IPC and half from higher Fmax. That would imply a max boost clock of ~6.2 GHz, which I think is do-able.

I think IPC might go up as much as 10% .... 15% on the outside and most of that will be due to improved memory controller and interconnect speeds offered by the new IOD (and higher bandwidth from DDR8000). I don't disagree with your clock estimate though.

It is entirely possible that Nova Lake will surprise us all though. Just as when AMD first went to chiplets, Zen 2 suffered until Zen 3 cleared it up. Imagine that ARL to NVL has the same jump?

 

[adroc_thurston]

I think that if Zen 6 comes out before Nova Lake, it will be 6.0Ghz .... maybe 6.2Ghz

irrelevant.

It is entirely possible that Nova Lake will surprise us all though

11% 1t, 60% nT. that's it.

 

[Saylick]

irrelevant.

11% 1t, 60% nT. that's it.

lol, that's one way to be technically truthful when claiming ">1.1 higher ST".

 

[Saylick]

I think IPC might go up as much as 10% .... 15% on the outside and most of that will be due to improved memory controller and interconnect speeds offered by the new IOD (and higher bandwidth from DDR8000). I don't disagree with your clock estimate though.

My statement of 20% ST gain for Zen 6 should be a safe floor, I think. The leaked roadmap slide said Zen 6 was 10%+ IPC uplift and ~6.2 GHz is almost at 10% Fmax increase (cumulative is 1.1*1.09 = 1.2x uplift). All it takes is a little bit more IPC and/or Fmax increase and you're comfortably in the 1.25x realm, which is solid.

 

[Thunder 57]

It is entirely possible that Nova Lake will surprise us all though. Just as when AMD first went to chiplets, Zen 2 suffered until Zen 3 cleared it up. Imagine that ARL to NVL has the same jump?

A big chunk of those gains were from moving to 2 x CCX's with split L3 to a since CCD with unifed L3. Nova Lake will still be 2 x 8P/16e core at best. They would have to fix their L3 problems and have the rumored massive version of it to have a chance of surprising us IMHO.

 

[adroc_thurston]

A big chunk of those gains were from moving to 2 x CCX's with split L3 to a since CCD with unifed L3

Oh no that only ever mattered in a bunch of video games.

 

[MS_AT]

btw, were there any leaks about private caches?

 

[adroc_thurston]

btw, were there any leaks about private caches?

For Zen6? Nothing ever happens.

 

[basix]

6.5 GHz would already be awesome. 7 GHz is a dream we still can be dreaming until Zen 6 sees the light of day, but if you bet your house on that, good luck.

+14% clock rate together witth ~10% IPC increase are still very respectable +25% ST performance increase. I would be happy with that. And when bigger L3$ and lower memory latency kicks in, it might be even more than that.

 

[adroc_thurston]

7 GHz is a dream we still can be dreaming until Zen 6 sees the light of day

ah no 7G is not happening.

 

[igor_kavinski]

Remember once upon a time when everyone talked about pipeline stalls or pipelines stages?

Whatever happened to that? I haven't seen mention of that since Core architecture came on the scene.

How many pipelines stages in Zen 2, 3, 4 and 5 and Raptor/Lion Cove and Grace/Skymont?

Is Zen 6 going to increase pipeline stages to hit higher frequencies?

 

[adroc_thurston]

Remember once upon a time when everyone talked about pipeline stalls or pipelines stages?

Whatever happened to that? I haven't seen mention of that since Core architecture came on the scene.

No one's doing 31 stage hyberbibelines anymore so whatever.

 

[igor_kavinski]

No one's doing 31 stage hyberbibelines anymore so whatever.

What are they doing then? I need perspective with respect to current architectures.

 

[adroc_thurston]

What are they doing then?

Not doing that?

I need perspective with respect to current architectures.

10-15 stages is the norm.

 

[poke01]

so with Nova lake rumoured to be >1.1x, Zen6 is likely >1.2x. well, i hope it is

 

[Thunder 57]

What are they doing then? I need perspective with respect to current architectures.

I don't think that information is as readily available anymore. With Sandy Bridge it was 14-19 (variable because of the uop cache).

Haswell leaves the overall pipeline untouched. It's still the same 14 - 19 stage pipeline that we saw with Sandy Bridge depending on whether or not the instruction is found in the uop cache (which happens around 80% of the time).

I thought I read at some point ADL was a few more maybe 17 - low 20's. I'd bet Zen is in a similar range.

Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel

www.anandtech.com

 

[adroc_thurston]

I'd bet Zen is in a similar range.

13-18 for Zen3/4 and 14-18 for Zen5.

 

[DavidC1]

I don't think that information is as readily available anymore. With Sandy Bridge it was 14-19 (variable because of the uop cache).

Sandy Bridge is 14-18. Then then said nothing about the pipeline stage until Golden Cove which increased it by 1, so it should be 15-19. In Nehalem they increased it to 16 from 14, and it came with Turbo so it's a clock focus. Uop cache allowed Sandy Bridge to clock high and reduce the penalty that comes from the increased stage(remember Core 2 was 14). Essentially a sane Netburst.

 

[adroc_thurston]

13-18 for Zen3/4 and 14-18 for Zen5.

No I think that's wrong also.
It's 11-18 and 12-18.

 

[Saylick]

No I think that's wrong also.
It's 11-18 and 12-18.

Pretty complicated decode stage if it alone takes up 6 or 7 clocks.

 

[OneEng2]

irrelevant.

I haven't yet figured out if you are lazy, or just lack the ability to complete a sentence ..... rather on reply with information supporting your incredibly useless one-word-replies.

Care to explain why competition at the time of launch is irrelevant?

Is Zen 6 going to increase pipeline stages to hit higher frequencies?

I am not entirely certain what happened, but I can guess.

The reason pipeline stages were increased was due to keeping the transistor timing within a stage in sync. As soon as one parallel path in the stage got out of clock sync with the others, clock scaling failed.

Intel decided that it was a good idea to clock to the moon even though adding stages lowered IPC.

I believe what happened is that the thermal limit to clock speed got reached before the pipeline stage limitation.

Additionally, my guess is that better fabrication techniques may exist today to make the transistors more uniform in their timing ..... making the pipeline stage alignment better and further moving the thermal limit before the pipeline stage alignment limit.

If someone else has a better explanation, I am all ears.

As I was previously saying, even IF ZEN 6 had the ability to clock to 7Ghz, it is highly unlikely that AMD would push it to those speeds for financial reasons.

This is another reason to hope for a good Nova Lake launch IMO.

 

[poke01]

haven't yet figured out if you are lazy, or just lack the ability to complete a sentence

His words are more coherent than your essays 😝