10-15%.It says nothing about how much extra top-end clockspeed Zen6 will get vs Zen5
So (sorry if this is redundant) with ~10% IPC improvement and 10-15% clockspeed increase, Zen6 should see an ST improvement of ~21%-26.5%10-15%.
What about heat density? Isn't that going to increase with the smaller CCDs? Is AMD going to develop a better TIM solution yet again for better heat dissipation?10-15%.
yeah back to The Usual(tm).Zen6 should see an ST improvement of ~21%-26.5%
Not a problem.What about heat density?
They're not smaller, 70-80mm^2 range is the usual.Isn't that going to increase with the smaller CCDs?
wdym hype train, Zen4 was 29% 1t with like 13% ppc and 16% freq.I think we are fueling the hype train at this point with too much hopium.
Yeah if physics doesn't get in the way.wdym hype train, Zen4 was 29% 1t with like 13% ppc and 16% freq.
it already did, N3 and N2 both have lower Vmax.Yeah if physics doesn't get in the way.
Qualcomm will be shipping 5GHz CPUs in Androids with N3P later this year. These are PHONES.Honestly, I'll be EXTREMELY impressed if Zen 6 manages even 6.2GHz. That is an amazingly high number to deem "safe" for millions of shipping CPUs. I wouldnt be surprised at all if 6.0 or 5.9 is all it gets. These >6.2GHz claims all have the echoes of Zen 5 +40% IPC. Hype train alert.
Think about this. If Nova Lake is using N2 as well, why is its ST limited to 1.1x? If N2 allows for >6.2GHz, Nova Lake will achieve that based on frequency alone.
Lisa Su herself presented a slide about Epyc Venice detailing a 1.7x improvement.Honestly, I'll be EXTREMELY impressed if Zen 6 manages even 6.2GHz. That is an amazingly high number to deem "safe" for millions of shipping CPUs. I wouldnt be surprised at all if 6.0 or 5.9 is all it gets. These >6.2GHz claims all have the echoes of Zen 5 +40% IPC. Hype train alert.
Think about this. If Nova Lake is using N2 as well, why is its ST limited to 1.1x? If N2 allows for >6.2GHz, Nova Lake will achieve that based on frequency alone.
That 1.7x perf number is for Venice Dense with 256 cores vs Turin Dense with 192 cores.Lisa Su herself presented a slide about Epyc Venice detailing a 1.7x improvement.
Given the expected 1.5x core count increase that leaves roughly 1.135x improvement from IPC and clock.
Don't let anyone dissuade you from this argument. Designs have been thermal density limited for quite some time. You are likely correct. Additionally, power creation increases super linearly with clock speed..... and once you reach a certain point, it just plain skyrockets.What about heat density? Isn't that going to increase with the smaller CCDs? Is AMD going to develop a better TIM solution yet again for better heat dissipation?
I think we are fueling the hype train at this point with too much hopium.
Damn those laws of physics!Yeah if physics doesn't get in the way.
Possibly so. I also think that all this doom and gloom on NVL is premature. ARL is severely impacted by horrendous latency. I suspect that a good amount of IPC is easily accessible just by bringing this down.Honestly, I'll be EXTREMELY impressed if Zen 6 manages even 6.2GHz. That is an amazingly high number to deem "safe" for millions of shipping CPUs. I wouldnt be surprised at all if 6.0 or 5.9 is all it gets. These >6.2GHz claims all have the echoes of Zen 5 +40% IPC. Hype train alert.
Think about this. If Nova Lake is using N2 as well, why is its ST limited to 1.1x? If N2 allows for >6.2GHz, Nova Lake will achieve that based on frequency alone.
For Venice, it is all about power efficiency. It will never be clock limited.... but I like your math. This does give us a look into the IPC gains we can expect from Zen 6. I think it is fair to expect a 13.5% improvement between clock speed and IPC improvements. These hopes and dreams of 25% are more than a little out there IMO.Lisa Su herself presented a slide about Epyc Venice detailing a 1.7x improvement.
Given the expected 1.5x core count increase that leaves roughly 1.135x improvement from IPC and clock.
Qualcomm will be shipping 5GHz CPUs in Androids with N3P later this year. These are PHONES.
A desktop CPU on N2 with a huge heatsink can easily do >6GHz on N2.
Thats far from fact at this time. The >5GHz speeds are only a rumor, opposing another rumor that claimed the exact opposite, low freqs and higher IPC. Further, they are rumored to be employed for testing/validation only. Im hugely skeptical we'll be seeing 5GHz in phones anytime soon.Qualcomm will be shipping 5GHz CPUs in Androids with N3P later this year. These are PHONES.
A desktop CPU on N2 with a huge heatsink can easily do >6GHz on N2.
Yes, I did say Qualcomm. The opposing rumour from the same person talks about ARM aiming for higher IPC and low frequency.The >5GHz speeds are only a rumor, opposing another rumor that claimed the exact opposite, low freqs and higher IPC
My gut feeling is that there are trade offs in all things. Each architecture has targeted certain goals over others and achieved supremacy .... in some respects and lacked in others.Indeed, the ARM forces, which are making it difficult to expand the IPC due to the improvements in architecture...
I've never done it before I'm trying to increase the clock
On the contrary, the x86 forces are aiming to improve the IPC this time because they have increased their clocks...
However, most of the architecture improvements to improve the IPC have been done...My gut feeling is that there are trade offs in all things. Each architecture has targeted certain goals over others and achieved supremacy .... in some respects and lacked in others.
Generally speaking increasing clocks comes at the expense of power draw (for sure) and sometimes IPC (if the number of pipeline stages are increased).
I think where most of the designs are now is getting the best performance per power as many designs find themselves either power limited, or thermally limited.
Clock speed is just not a great tool to reach for when that is the case .
Lisa Su herself presented a slide about Epyc Venice detailing a 1.7x improvement.For Venice, it is all about power efficiency. It will never be clock limited.... but I like your math. This does give us a look into the IPC gains we can expect from Zen 6. I think it is fair to expect a 13.5% improvement between clock speed and IPC improvements. These hopes and dreams of 25% are more than a little out there IMO.
The speed of software halves every 18 months.
AFAIK EPYCs do not casually run at 5.7GHz... The quoted 1.7x figure is surely for a top model which means a strongly thermally/power limited SKU. That means 2nm should allow higher real frequency than 2.25/3.7GHz of Bergamo.Lisa Su herself presented a slide about Epyc Venice detailing a 1.7x improvement.
Given the expected 1.34x (256 vs 192) core count increase that leaves roughly 1.275x improvement from IPC and clock.
Suddenly we're above that +25% performance increase per core you call "hope and dreams" 😅
To reach +27.5 performance with a +10% IPC increase, you need a ~ 1.16% clockspeed increase
5.7ghz * 1.16 = 6.612ghz
Do note this is calculated from conservative epyc figures
Eloquently put.Mind you that the Zen 5's "server IPC improvement" led to that laughable Zen 5 +40% IPC hypetrain.
6GHz+ is not unreasonable for peak 1T clock. It's 2 node jumps, for 400 MHz increase over Zen5 (to reach 6.1GHz which meets the 6GHz+ criteria). If AMD suddenly changed the philosophy and decided to go for a higher ipc instead of higher freq, then yes, clock bump would be unrealistic. But the leaked ipc improvement slide suggests more of the same. This says nothing about the sustained MT clocks at reasonable power levelsThat's why I will disregard any talk about 6+ GHz frequencies