Question Zen 6 Speculation Thread

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Doug S

Diamond Member
Feb 8, 2020
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I think it's just the timeline, Apple likes sticking to a product launch calendar and it's won't be ready for Apple's major launches in 2026. Also AMD is probably more willing to delay product launch for last-minute delays.

There have been conflicting reports about who will be getting early N2 nodes. I agree Apple's product launch schedule doesn't line up very well with N2's mass production schedule, but don't forget about Apple's internal consumption. They may not need N2 out of the gate for iPhone and Mac chips (other than perhaps a few million M6s if they want to do an early release of iPad Pro like with M4) but they could end up using a lot of wafers for their servers. Since those don't ship to customers they wouldn't be sensitive to potential delays, and Apple can switch those wafer allocations to iPhone/Mac SoCs when the release calendar dictates.

Unless Apple didn't prepay this time they will have a large allocation of N2 wafers. They wouldn't let the value of that prepayment go to waste, they'll have to something for TSMC to fab even if it isn't going into something we can buy.
 

HurleyBird

Platinum Member
Apr 22, 2003
2,798
1,518
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What you're doing here is like trying to extrapolate improvement in 0-60 time of a car based on reports of a 70% gain in towing capacity of a truck that uses the same engine.

It's more like trying to extrapolate the change in 0-100 time of the new model year 2-door from the change in 0-60 time of the new model year 4-door.
 
Reactions: OneEng2

OneEng2

Senior member
Sep 19, 2022
663
906
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Yeah. Don't see any reason why AMD would skip N3P or N3X.
Agree. I think the majority of the disagreement is on what parts will get N2. Everyone agrees that Zen 6c Venice will get N2. I wouldn't be surprised if Zen 6 full Venice gets it as well. The rest? Debatable, but certainly not out of the realm of possibility.
Wouldn't N2 be severely capacity constrained?
Yes, but I think it depends on what orders exist at what time. While others here seem to think that TSMC can just turn on N2 and supply 1/3rd of the entire market over night, I tend to agree with your assessment that AMD will supply lots more chips on N3P than they do on N2.
Only the top tier parts have it. The bulk of mass production is on n3 class nodes. All they need to produce is diy desktop and server. They're also the first and only customer initially.
I don't completely disagree with you. I am wondering what the cost of bringing a 12c CCD to both N2 and N3P costs. If it isn't that bad, and AMD can easily mix and match without significantly high cost and timing, then there is no reason we wont see a mix of the same CCD's produced on different nodes for different markets. Of course, this is making the BIG assumption that a 12c N2 CCD would outperform (out clock) a 12c N3P CCD. That may not be the case.

I have zero doubt that N2 will provide much better PPA which is super critical in DC. In high performance desktop, my opinion is that it is much more important to get a few cores to top clock speeds.

Laptop is a different story.
But pricing might depend on what performance Intel can get out of the big last level cache variants.
I totally agree that pricing AND performance will likely be dependent on what Intel can bring to bear for competition.
It's bittersweet because obviously most of us wish they weren't THAT successful

With great success comes exorbitant prices!
100% agree.

It is true that AMD have been raising their profit margins by a combination of their HUGE increase in DC market .... and much of it at the high end (although the new low end EPYC's look to squash the low end DC also) and the high end DIY parts.

From a near term profit standpoint, this makes sense; however, at the end of the day volume is very important. Being able to make larger orders gives AMD more leverage in pricing. Larger volume lets AMD amortize their dev costs over more units, higher revenue lets AMD invest more in future designs, etc, etc.

Many a company in the past has gone by the wayside by ignoring volume. AMD doesn't appear poised to repeat this mistake.

This is why I suspect there will be lots more production of Zen 6 on N3P than many in this forum believe.
 

Kepler_L2

Senior member
Sep 6, 2020
857
3,500
136
Idk how we're still debating the nodes

Venice (MS server) uses N2P
Venice-Dense (Cloud server) uses N2P
Olympic Ridge (desktop) uses N2P
Gator Range (high-end laptop) uses N2P
Medusa Point 1 (premium laptop) uses both N2P+N3P for top SKUs and N3P only for lower end SKUs

All of this information has been given from AMD to OEMs and AIBs.
 

poke01

Diamond Member
Mar 8, 2022
3,649
4,965
106
M
Idk how we're still debating the nodes

Venice (MS server) uses N2P
Venice-Dense (Cloud server) uses N2P
Olympic Ridge (desktop) uses N2P
Gator Range (high-end laptop) uses N2P
Medusa Point 1 (premium laptop) uses both N2P+N3P for top SKUs and N3P only for lower end SKUs

All of this information has been given from AMD to OEMs and AIBs.
Is there no vanilla N2?
 

OneEng2

Senior member
Sep 19, 2022
663
906
106
The only thing getting N3P is the Mobile SKU
Link please.
That makes no sense. N3P is the high perf node, no? You would want mobile to be on N2 for the highest power efficiency.
Everyone (most everyone) is assuming that N2 will clock higher than N3P. I am with you in expressing doubt on that subject.
Idk how we're still debating the nodes

Venice (MS server) uses N2P
Venice-Dense (Cloud server) uses N2P
Olympic Ridge (desktop) uses N2P
Gator Range (high-end laptop) uses N2P
Medusa Point 1 (premium laptop) uses both N2P+N3P for top SKUs and N3P only for lower end SKUs

All of this information has been given from AMD to OEMs and AIBs.
Link please.
 
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poke01

Diamond Member
Mar 8, 2022
3,649
4,965
106
I can’t wait for Zen6, it will shut up the ARM bros for a bit.

I am 100% hopeful of Zen 6 achieving >6GHz. It’s only 400Mhz away. Doable via NanoFlex
 
Reactions: Tlh97 and OneEng2

Kepler_L2

Senior member
Sep 6, 2020
857
3,500
136
There's nicer ways of saying "that information is proprietary and hasn't been officially released to the public/media outlets". Unless it has, in which case it's certainly appropriate for @OneEng2 to request links corroborating statements e.g. he who makes the claim must provide the evidence.
I'm sure someone will leak it on chinese forums as they usually do
 

Josh128

Golden Member
Oct 14, 2022
1,021
1,499
106
Once again, AMD has never, ever used a bleeding edge node for its desktop CCDs. Why would they start now? What is the V-cache supposed to use, 5nm? GPUIOD?? Y'all do realize that 2nm desktop CPUs would have to be insanely expensive, right?
 

DrMrLordX

Lifer
Apr 27, 2000
22,661
12,586
136
Once again, AMD has never, ever used a bleeding edge node for its desktop CCDs. Why would they start now?

Why not?

What is the V-cache supposed to use, 5nm? GPUIOD??

If the past is any indicator, AMD won't start with v-cache parts and it will take time before TSMC can offer that style of packaging on N2-family nodes. As to what node will be used for the cache tiles, who knows? N4P? N3P?

Y'all do realize that 2nm desktop CPUs would have to be insanely expensive, right?
Premium parts come with premium prices.
 

Tuna-Fish

Golden Member
Mar 4, 2011
1,639
2,447
136
There is room to raise prices on the high end ($479 MSRP for the 9800X3D was absurd, had AMD set it at $499 they would have sold exactly as many and added $20 of margin to each sale) , I worry more about the low end.
 
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