Point being is that 96M is already enough for hot data, and mem hits won't stop until games fit directly into cache (which they won't).
No it isn't. AMD didn't provide iGPUs to those companies for their consoles.They don’t?? IGPU is reason why AMD has Sony and MS contracts.
That's why you don't need a 2stack v-cacheExcellent observations. Shows there is a lot of brand loyalty, enduring instability of their (loony) tuned systems, up to a point of ridicule and surrender (with Arrow Lake).
In the meantime, there is also a lot of deferrals of purchases, until their favorite vendor releases a CPU that is not laughable. So, you will see people hanging onto their Alder Lake, Raptor Lake as long as they can, arguing that CPU performance does not matter, trying to hold out for Nova Lake.
Which, means, there will be a lot of pent-up demand when Nova Lake is released, and margin of Zen 6 vs. Nova Lake will matter. If it takes 2-hi V-Cache, AMD will release it to hold their current margin.
Lisa will have complete victory at hand, but wait, @adroc_thurston says Lisa will rather nickel and dime than go for full victory.
Are you trying to mock Alder Lake?there is loyalty in every part of every industry, it takes long repeated stuff ups to break a 30 year old pattern.
So far since Skylake Intel f upped a lot.
Nope, Alder lake was good.Are you trying to mock Alder Lake?
They certainly make mistakes, but there are some good ones tooNope, Alder lake was good.
Yes, so very large relatively low latency L3 cache would be niceThat was Very True but then RTRT happened.
Does not need to be iGPU - make it 600 sq mm GPU + 3D cache, that should move the needle on UE5 perfa) cost
b) no one actually uses iGPUs.
It's valid forever until the games neatly fit their workset into a 240M-sized slab of L3 (which is never).
however source is MLID
Around 1 CCD, isn't it 144MB including the original L3 cache?Zen 6 Ryzen 10000X3D May Feature Advanced Multi-Layer 192 MB X3D Cache
AMD’s next-generation Zen 6 CPU architecture is expected to incorporate a substantial upgrade in cache capacity through advanced 3D V-Cache technology. The rumored design includes stackable layers of 96 MB cache chips, which could double the current cache size to 192 MB per chiplet compared to...www.guru3d.com
pretty much inline with what everyone is saying in this thread.
however source is MLID so lots of salt needed.
I am near the sea where salt is extractedZen 6 Ryzen 10000X3D May Feature Advanced Multi-Layer 192 MB X3D Cache
AMD’s next-generation Zen 6 CPU architecture is expected to incorporate a substantial upgrade in cache capacity through advanced 3D V-Cache technology. The rumored design includes stackable layers of 96 MB cache chips, which could double the current cache size to 192 MB per chiplet compared to...www.guru3d.com
pretty much inline with what everyone is saying in this thread.
however source is MLID so lots of salt needed.
This is what I thought as well.Around 1 CCD, isn't it 144MB including the original L3 cache?
Just because it CAN be done doesn't mean it WILL be done. The AMD person MLID interviewed was clear to say that it's POSSIBLE to stack more than 1-high for the 3D V-cache, but "possibilities" do not nor should not automatically mean a product will come to market that features it. Of course, the word "nuance" doesn't exist in the dictionary for tech publications, so they'll run to the press with anything.Zen 6 Ryzen 10000X3D May Feature Advanced Multi-Layer 192 MB X3D Cache
AMD’s next-generation Zen 6 CPU architecture is expected to incorporate a substantial upgrade in cache capacity through advanced 3D V-Cache technology. The rumored design includes stackable layers of 96 MB cache chips, which could double the current cache size to 192 MB per chiplet compared to...www.guru3d.com
pretty much inline with what everyone is saying in this thread.
however source is MLID so lots of salt needed.
I agree and don't think they will double stack on the desktop chips and will save that for server.Just because it CAN be done doesn't mean it WILL be done. The AMD person MLID interviewed was clear to say that it's POSSIBLE to stack more than 1-high for the 3D V-cache, but "possibilities" do not nor should not automatically mean a product will come to market that features it. Of course, the word "nuance" doesn't exist in the dictionary for tech publications, so they'll run to the press with anything.
This is what I thought as well.
we are getting a few different guesses on what the size of it will be but my money is on 144MB.
What evidence do we have that they ever double stacked for EPYC? Someone mentioned this earlier in the thread as if it was common knowledge.
Just like the Dual Cache 5900X prototypeIt may (or may not) have existed inside AMD's labs, but never made it out of there
They developed the ability to stack >1-Hi, but it was never brought to market. I don't even think there's an engineering sample floating in the wild with 2-Hi stack.What evidence do we have that they ever double stacked for EPYC? Someone mentioned this earlier in the thread as if it was common knowledge.
Not happening.Yes, so very large relatively low latency L3 cache would be nice
oh, AMD client gfx ghetto is not allowed to build anything this huge by Lisa herself. They're doomed to nothingness.Does not need to be iGPU - make it 600 sq mm GPU + 3D cache
Raster, yes.According to AMD that should be enough to cache GPU stuff very effectively at 4k res, which in turn can support more compute.
oh, AMD client gfx ghetto is not allowed to build anything this huge by Lisa herself. They're doomed to nothingness.
Sony is irrelevant, they're just a semicustom vendor.What, Sony won't let them?
I like your enthusiasm guys but you are expecting too much lol, we're already getting :
- Higher clock speed
- Higher memory speed support
- More cores
- More cache
Not even talking about IPC but let's be conservative and say 8-10%, do you really think AMD will feel pressured to add one layer to its L3 stacking technology ?
Regardless we're already getting more L3 even before they add another layer, it will cover some more edges cases but we're soon reaching points of diminishing returns.
It's cool to know that they're able to do that but we shouldn't read too much into it, it's not like Intel can really do anything about it...