Question Zen 6 Speculation Thread

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DrMrLordX

Lifer
Apr 27, 2000
22,663
12,591
136
Point being is that 96M is already enough for hot data, and mem hits won't stop until games fit directly into cache (which they won't).

Nethack to the rescue!!! Seriously though, people used to do some really innovative stuff in tiny amounts of memory. I remember someone doing an (admittedly gimmicky) entire first-person shooter that would fit in 640k. It would be interesting to see what modern developers could do with a ~96MB limit.

They don’t?? IGPU is reason why AMD has Sony and MS contracts.
No it isn't. AMD didn't provide iGPUs to those companies for their consoles.
 

Io Magnesso

Senior member
Jun 12, 2025
377
107
71
Excellent observations. Shows there is a lot of brand loyalty, enduring instability of their (loony) tuned systems, up to a point of ridicule and surrender (with Arrow Lake).

In the meantime, there is also a lot of deferrals of purchases, until their favorite vendor releases a CPU that is not laughable. So, you will see people hanging onto their Alder Lake, Raptor Lake as long as they can, arguing that CPU performance does not matter, trying to hold out for Nova Lake.

Which, means, there will be a lot of pent-up demand when Nova Lake is released, and margin of Zen 6 vs. Nova Lake will matter. If it takes 2-hi V-Cache, AMD will release it to hold their current margin.

Lisa will have complete victory at hand, but wait, @adroc_thurston says Lisa will rather nickel and dime than go for full victory.
That's why you don't need a 2stack v-cache
 

Win2012R2

Senior member
Dec 5, 2024
959
931
96
a) cost
b) no one actually uses iGPUs.
Does not need to be iGPU - make it 600 sq mm GPU + 3D cache, that should move the needle on UE5 perf

What cost anyway? AMD puts 64 MB on 7600X3Ds now, it can't cost much - make a cracking top end GPU with it and sell it for $1k.

It's valid forever until the games neatly fit their workset into a 240M-sized slab of L3 (which is never).

According to AMD that should be enough to cache GPU stuff very effectively at 4k res, which in turn can support more compute.
 
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Makaveli

Diamond Member
Feb 8, 2002
4,952
1,544
136

pretty much inline with what everyone is saying in this thread.

however source is MLID so lots of salt needed.
 

Io Magnesso

Senior member
Jun 12, 2025
377
107
71

pretty much inline with what everyone is saying in this thread.

however source is MLID so lots of salt needed.
Around 1 CCD, isn't it 144MB including the original L3 cache?
 
Reactions: Tlh97 and Makaveli

511

Platinum Member
Jul 12, 2024
2,727
2,637
106

pretty much inline with what everyone is saying in this thread.

however source is MLID so lots of salt needed.
I am near the sea where salt is extracted
 

Saylick

Diamond Member
Sep 10, 2012
3,907
9,073
136

pretty much inline with what everyone is saying in this thread.

however source is MLID so lots of salt needed.
Just because it CAN be done doesn't mean it WILL be done. The AMD person MLID interviewed was clear to say that it's POSSIBLE to stack more than 1-high for the 3D V-cache, but "possibilities" do not nor should not automatically mean a product will come to market that features it. Of course, the word "nuance" doesn't exist in the dictionary for tech publications, so they'll run to the press with anything.
 

Makaveli

Diamond Member
Feb 8, 2002
4,952
1,544
136
Just because it CAN be done doesn't mean it WILL be done. The AMD person MLID interviewed was clear to say that it's POSSIBLE to stack more than 1-high for the 3D V-cache, but "possibilities" do not nor should not automatically mean a product will come to market that features it. Of course, the word "nuance" doesn't exist in the dictionary for tech publications, so they'll run to the press with anything.
I agree and don't think they will double stack on the desktop chips and will save that for server.
 

Josh128

Golden Member
Oct 14, 2022
1,021
1,500
106
What evidence do we have that they ever double stacked for EPYC? Someone mentioned this earlier in the thread as if it was common knowledge.
 

Saylick

Diamond Member
Sep 10, 2012
3,907
9,073
136
What evidence do we have that they ever double stacked for EPYC? Someone mentioned this earlier in the thread as if it was common knowledge.
They developed the ability to stack >1-Hi, but it was never brought to market. I don't even think there's an engineering sample floating in the wild with 2-Hi stack.
 
Reactions: Io Magnesso

adroc_thurston

Diamond Member
Jul 2, 2023
6,038
8,515
106
Yes, so very large relatively low latency L3 cache would be nice
Not happening.
Does not need to be iGPU - make it 600 sq mm GPU + 3D cache
oh, AMD client gfx ghetto is not allowed to build anything this huge by Lisa herself. They're doomed to nothingness.
According to AMD that should be enough to cache GPU stuff very effectively at 4k res, which in turn can support more compute.
Raster, yes.
RTRT, no, hot data will be sitting inside shader core LDS and the scene actual will be uncached in gmem.
 

Doge

Junior Member
Jul 8, 2025
1
8
36
I like your enthusiasm guys but you are expecting too much lol, we're already getting :

- Higher clock speed
- Higher memory speed support
- More cores
- More cache

Not even talking about IPC but let's be conservative and say 8-10%, do you really think AMD will feel pressured to add one layer to its L3 stacking technology ?
Regardless we're already getting more L3 even before they add another layer, it will cover some more edges cases but we're soon reaching points of diminishing returns.

It's cool to know that they're able to do that but we shouldn't read too much into it, it's not like Intel can really do anything about it...
 

511

Platinum Member
Jul 12, 2024
2,727
2,637
106
I like your enthusiasm guys but you are expecting too much lol, we're already getting :

- Higher clock speed
- Higher memory speed support
- More cores
- More cache

Not even talking about IPC but let's be conservative and say 8-10%, do you really think AMD will feel pressured to add one layer to its L3 stacking technology ?
Regardless we're already getting more L3 even before they add another layer, it will cover some more edges cases but we're soon reaching points of diminishing returns.

It's cool to know that they're able to do that but we shouldn't read too much into it, it's not like Intel can really do anything about it...

Both the vendors are doing the same tbh in this gen plus new packing tech as well for Desktop from both and let's not forget the 70 TOPS Die Waste Unit that we will be getting
 
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