While it's possible that you could break up a CPU core between layers, there's a bit of latency that makes that problematic with our current methods. I could see in maybe half a decade where they would identify the worst hot spots on the core and arrange it so that they could be on an upper layer, with the less thermally dense areas on a lower layer, then the L2 layer below that, then all of that on an L3 layer. There's the potential that the various layers of the core can be on completely different lithography generations.
Far more likely, though, is the next step being Core components stacked on L2, stacked on L3, stacked on I/O. The L3 layer can be designed around high energy efficiency and density, the L2 area can be designed around moderate density and efficiency but very high performance, and the core die can be balanced as needed. Different layers could be swapped around for different applications, like a core die that's planned for maximum density and efficiency for mobile use, and another planned for maximum performance for desktop use.