Recent content by Tigerick

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    Discussion Apple Silicon SoC thread

    I still think upcoming iPad Pro will use M3 only, not M4. Let's see..
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Yep, Intel maybe late to join the fight but they won't miss: STX 4+8 HT 16CU vs PTL-H 4+8+4 noHT 12 XE KRK 4+4 8CU vs PTL-U 4+4 4 XE
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    Discussion Apple Silicon SoC thread

    You should check the leaks by Mark Gurman
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Due to PTL-U GPU is using 4 XE cores made by Intel 3, the graphics performance would be slower than LNL. That's mean PTL-U is positioned slightly below LNL
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    And remove e cores again to get 4+4 configuration back in PTL-U..
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Good question, I just got reply from my source. You are not going to believe it. PTL-U going to use 4+0+4 configuration. :eek: Maybe Intel wants to treat PTL-U as Lunar Laker successor...
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    I know it sounds better, but Intel has changed the name, so what should we refer IF or IFS?
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    Discussion Apple Silicon SoC thread

    Eug, you do know the advantage of N3B process. Have you ever thought about what Apple going to upgrade the upcoming M4 SoC? I am expecting 2 more e-cores, 2 more GPU cores and SLC cache expansion. Not to mention the upgrades of NPU TOPS. Why does Apple switching to different design and lower...
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    Let's see: ARL-U's tCPU Sierra Forest Granite Rapids PTL's 4Xe tGPU Upcoming NV ARM SoC Yep, IF will keep expanding IP of Intel 3 process. It's going to be long term process for IF.
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    You should use the term used to cause due to 4-tile design, Meteor Lake is having worst memory latency as tested here. I don't think ARL will change that, maybe PTL with integrated MC will let Intel regain the leadership.
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Then ignore me, thank you
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Ho, you should check GB202's SM amount. And if my speculation is correct, upcoming GB203 should come with 144SM and GB205 should come with 80SM. Go figure...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Let's try to combine RDNA4 and RDNA5 in the table below: Codename Base Die WGP CU GDDR6 Memory Speed Memory BW RDNA4 N44 1 16 32 16GB 128-BIT 18 Gbps 288 GB/s N48 1 32 64 16GB 256-BIT 18 Gbps 576 GB/s RDNA5 GDDR7 N52 2 96 192 16GB 256-BIT 32 Gbps...
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    Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

    @DavidC1 Someone looking for you :p
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    News Intel 1Q24 Earnings Report

    Hard to say cause with upcoming ARL and LNL are all requiring packaging, do you believe Intel is not planning ahead?
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