Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

Tigerick · Aug 22, 2022

As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.

Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

Model	Code-Name	Date	TDP	Node	Tiles	Main Tile	CPU	LP E-Core	LLC	GPU	Xe-cores
Core Ultra 100U	Meteor Lake	Q4 2023	15 - 57 W	Intel 4 + N5 + N6	4	tCPU	2P + 8E	2	12 MB	Intel Graphics	4
?	Lunar Lake	Q4 2024	17 - 30 W	N3B + N6	2	CPU + GPU & IMC	4P + 4E	0	8 MB	Arc	8
?	Panther Lake	Q1 2026 ?	?	Intel 18A + N3E	3	CPU + MC	4P + 8E	4	?	Arc	12

Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

	Meteor Lake	Arrow Lake (20A)	Arrow Lake (N3B)	Arrow Lake Refresh (N3B)	Lunar Lake	Panther Lake
Platform	Mobile H/U Only	Desktop Only	Desktop & Mobile H&HX	Desktop Only	Mobile U Only	Mobile H
Process Node	Intel 4	Intel 20A	TSMC N3B	TSMC N3B	TSMC N3B	Intel 18A
Date	Q4 2023	Q1 2025 ?	Desktop-Q4-2024 H&HX-Q1-2025	Q4 2025 ?	Q4 2024	Q1 2026 ?
Full Die	6P + 8P	6P + 8E ?	8P + 16E	8P + 32E	4P + 4E	4P + 8E
LLC	24 MB	24 MB ?	36 MB ?	?	8 MB	?
tCPU	66.48
tGPU	44.45
SoC	96.77
IOE	44.45
Total	252.15

Intel Core Ultra 100 - Meteor Lake

As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

gdansk · Feb 14, 2024

Advanced packaging seems inevitable so being at the cutting edge there is likely synonymous with the cutting edge of performance. And it should provide Intel a more compelling product in the long term (though as you say it doesn't seem too likely with ARL-S).

H433x0n · Feb 14, 2024

gdansk said:
Advanced packaging seems inevitable so being at the cutting edge there is likely synonymous with the cutting edge of performance. And it should provide Intel a more compelling product in the long term (though as you say it doesn't seem too likely with ARL-S).

Eh, a <=200mm2 die doesn’t benefit nor require to be a chiplet. Even when we move to High NA EUV that’s still well within the reticle limit.

gdansk · Feb 14, 2024

H433x0n said:
Eh, a <=200mm2 die doesn’t benefit nor require to be a chiplet. Even when we move to High NA EUV that’s still well within the reticle limit.

I reckon we're all heading toward M2 Ultra (huge multi-chip GPU with small CPU on-board) and stacked LLC eventually. And so the combined die size will be much larger.

branch_suggestion · Feb 15, 2024

H433x0n said:
I don’t get the hype over the packaging. There’s a high probability that the packaging will be the cause for ARL-S having poor gaming performance.

Chiplets, tiles, whatever you want to call it is always a compromise solution in client products. It’s not a feature or impressive tech - it’s there to save money at the expense of a worse product.

SoIC stacked cache is better in some ways to the same amount of cache on a mono die. Or logic stacked upon cache, the wire distances are shorter and the surface area gains on the package floor are really nice. MI300 vs H100 illustrates this nicely.

adroc_thurston · Feb 15, 2024

gdansk said:
I reckon we're all heading toward M2 Ultra (huge multi-chip GPU with small CPU on-board)

no? console SoCs are niche.

gdansk said:
stacked LLC eventually.

That's far away from being mainstream.

gdansk · Feb 15, 2024

adroc_thurston said:
no? console SoCs are niche.

That's far away from being mainstream.

Sorry, by "we" I mean people like me who waste money on 4090s and housefire CPUs that can run them.
To which Apple (and MI300A?) presents a compelling vision of the future, a power-saving future with much larger unified memory. And I don't see how you unify big GPU + fast CPU and larger caches without advanced packaging even in the high-end consumer space.

& hence the eventually. Because I think this is something Intel will do too.

adroc_thurston · Feb 15, 2024

gdansk said:
To which Apple (and MI300A?) presents a compelling vision of the future

It's a console SoC with all the limitations (the future of 10 years ago; you're welcome).
MI300A is its very own thing, completely unfeasible in client.

gdansk said:
a power-saving future with much larger unified memory.

Gobs of LPDDR is still puny bandwidth versus what GDDR benches (LPPDR currently maxes at 9.6GT/s for the freshest PoP stuff. GDDR7 starts at 28GT/s).
It's not an alternative to client dGP, not at all.

gdansk said:
And I don't see how you unify big GPU + fast CPU and larger caches without advanced packaging even in the high-end consumer space.

Larger caches are also unfeasible in client, SRAM scaling is dead-dead.
Apple Max stuff is like 48 megs of SLC, puny stuff relative to what dGPs ship (and their cache b/w yea).

gdansk said:
& hence the eventually. Because I think this is something Intel will do too.

They've killed both FCS1 APU and all the GT3 iGP configs.
So no, they're not doing that.

gdansk · Feb 15, 2024

adroc_thurston said:
Larger caches are also unfeasible in client, SRAM scaling is dead-dead.

And that's why the biggest chunk of SRAM will be on another chip. What's your confidentlly wrong solution to stalled SRAM scaling? Just not add more cache? Not happening.

Anyway, the rest of it isn't relevant to products in this thread they're all too near. But Intel will do it or they'll become irrelevant like Burroughs.

Henry swagger · Feb 15, 2024

Kepler_L2 said:
View attachment 93780
LNC looks like another dud.

You said rnda 3 will more efficient than lovelace.. you dn't know anything jester

adroc_thurston · Feb 15, 2024

gdansk said:
And that's why the biggest chunk of SRAM will be on another chip.

SoIC-X is not suitable for mainstream applications for like until 2029 or so (that's the optimistic view of things to come).

gdansk said:
What's your confidentlly wrong solution to stalled SRAM scaling?

SOT-MRAM.
Pure hopium but it's the only hail mary possible.

gdansk said:
Just not add more cache?

Yeah.
I mean AMD chopped LLC off across Navi3 parts for a good reason.

gdansk said:
But Intel will do it or they'll become irrelevant like Burroughs.

do what.
They canned all GT3 ADM parts and they also canned FCS1 APU.

gdansk · Feb 15, 2024

adroc_thurston said:
Yeah.
I mean AMD chopped LLC off across Navi3 parts for a good reason.

Not in a particularily interesting way but the point is to get it off chip.

adroc_thurston said:
do what.
They canned all GT3 ADM parts and they also canned FCS1 APU.

Foveros Direct etc. Someone had asked why one would be interested in advanced packaging for consumer parts. And it's because SRAM scaling is stalled/dead. Adding cache via stacked chips and moving cache off chip has already come to consumer parts. In this line Intel will follow (unless they're waiting on a 'hail mary' - that would be Intel-like planning).

adroc_thurston · Feb 15, 2024

gdansk said:
Not in a particularily interesting way but the point is to get it off chip

As in the capacity is down on bigger parts.

gdansk said:
Foveros Direct etc

Everything hybrid bonding with be meme volumes for a while.

gdansk said:
Someone had asked why one would be interested in advanced packaging for consumer parts

Consumer part is a huge umbrella and niche DIY gaming sticks are the tiniest part of it.

gdansk said:
Adding cache via stacked chips and moving cache off chip has already come to consumer parts.

Novelty DIY SKU with absolute joke volumes is not "has already come to consumer parts".
Until a $999 laptop part ships with hybrid bonding it's a meme.

gdansk · Feb 15, 2024

adroc_thurston said:
Novelty DIY SKU with absolute joke volumes

Mainly what we care about here thoughever.

adroc_thurston · Feb 15, 2024

gdansk said:
Mainly what we care about here thoughever.

Wholly irrelevant product segment.
Also, >we.
I'm here and all I care is laptop stuff.

gdansk · Feb 15, 2024

adroc_thurston said:
Wholly irrelevant product segment.
Also, >we.
I'm here and all I care is laptop stuff.

Anandtech has a strong DIY PC bias for some reason. And even outside of that the halo parts are the most intersting. Isn't that right, Strix Halo's #1 prophet?

But with MTL it's of course a less interesting use of multiple chips than, say, M2 Ultra or 7800X3D. And I can see why someone would look at MTL and say why would consumers care about this? Because Intel's new tile approach seems entirely about cost-saving rather than trying to offer new levels of performance. But that's only Intel's current state and their problem alone.

adroc_thurston · Feb 15, 2024

gdansk said:
And even then halo-est of halo parts are the most intersting.

No.
Mainstream/premium ULV mobile is funnier since it's a fun joust between MS insanity and IHV attempts at making a usable SoC.

gdansk said:
Isn't that right, Strix Halo's #1 prophet?

That one is fun for being future AMD client prototype and not much else.

FlameTail · Feb 15, 2024

r/PCMR vs r/hardware

gdansk · Feb 15, 2024

FlameTail said:
r/PCMR vs r/hardware

Not even close, I'm typing on a Mac.

FlameTail · Feb 15, 2024

gdansk said:
Not even close, I'm typing on a Mac.

r/hardware is inclusive of Macs

Tigerick · Feb 15, 2024

OK, here comes some leaks not from me but credential leaker about ARL & PTL:

ARL-H (6P+8E) comes with iGPU (Build by newer process, N4P) 8 Xe1 LPG+ cores clocking at 2.3GHz
ARL-HX (8P+16E, H and HX's tCPU are different dies) comes with 4 Xe cores
SoC has been updated to support WiFi7, still on N6
PTL-H's tCPU integrates with 4P+8E+4LPe without HT, SoC and MC
Here comes interesting part, PTL's tGPU comes with 12 Xe3 LPG core clocking at 2.5GHz. Yeah it is GT3 with 7.7 TF, slightly higher than Strix Point. And they are built on Intel 3+ process. Finally, IFS build tGPU.
ADM so far is dead.

FlameTail · Feb 15, 2024

Does PTL have the standard 128 bit memory bus?

Tigerick · Feb 15, 2024

FlameTail said:
Does PTL have the standard 128 bit memory bus?

Yeah

Tigerick · Feb 15, 2024

adroc_thurston said:
SoIC-X is not suitable for mainstream applications for like until 2029 or so (that's the optimistic view of things to come).

SOT-MRAM.
Pure hopium but it's the only hail mary possible.

Yeah.
I mean AMD chopped LLC off across Navi3 parts for a good reason.

do what.
They canned all GT3 ADM parts and they also canned FCS1 APU.

Look like GT3 is back with PTL. ADM is dead yea

FlameTail · Feb 15, 2024

Tigerick said:
Look like GT3 is back with PTL. ADM is dead yea

What is ADM? Adamantine?

Why does Adamantine need an abbreviation? You Intel fellows love abbreviations, eh?

uzzi38 · Feb 15, 2024

FlameTail said:
What is ADM? Adamantine?

Why does Adamantine need an abbreviation? You Intel fellows love abbreviations, eh?

That is definitely NOT just an Intel thing... more like an overarching tech world thing.

Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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