Discussion Intel Meteor, Arrow, Lunar & Panther Lakes Discussion Threads

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Tigerick

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As Hot Chips 34 starting this week, Intel will unveil technical information of upcoming Meteor Lake (MTL) and Arrow Lake (ARL), new generation platform after Raptor Lake. Both MTL and ARL represent new direction which Intel will move to multiple chiplets and combine as one SoC platform.

MTL also represents new compute tile that based on Intel 4 process which is based on EUV lithography, a first from Intel. Intel expects to ship MTL mobile SoC in 2023.

ARL will come after MTL so Intel should be shipping it in 2024, that is what Intel roadmap is telling us. ARL compute tile will be manufactured by Intel 20A process, a first from Intel to use GAA transistors called RibbonFET.



Comparison of upcoming Intel's U-series CPU: Core Ultra 100U, Lunar Lake and Panther Lake

ModelCode-NameDateTDPNodeTilesMain TileCPULP E-CoreLLCGPUXe-cores
Core Ultra 100UMeteor LakeQ4 202315 - 57 WIntel 4 + N5 + N64tCPU2P + 8E212 MBIntel Graphics4
?Lunar LakeQ4 202417 - 30 WN3B + N62CPU + GPU & IMC4P + 4E08 MBArc8
?Panther LakeQ1 2026 ??Intel 18A + N3E3CPU + MC4P + 8E4?Arc12



Comparison of die size of Each Tile of Meteor Lake, Arrow Lake, Lunar Lake and Panther Lake

Meteor LakeArrow Lake (20A)Arrow Lake (N3B)Arrow Lake Refresh (N3B)Lunar LakePanther Lake
PlatformMobile H/U OnlyDesktop OnlyDesktop & Mobile H&HXDesktop OnlyMobile U OnlyMobile H
Process NodeIntel 4Intel 20ATSMC N3BTSMC N3BTSMC N3BIntel 18A
DateQ4 2023Q1 2025 ?Desktop-Q4-2024
H&HX-Q1-2025
Q4 2025 ?Q4 2024Q1 2026 ?
Full Die6P + 8P6P + 8E ?8P + 16E8P + 32E4P + 4E4P + 8E
LLC24 MB24 MB ?36 MB ??8 MB?
tCPU66.48
tGPU44.45
SoC96.77
IOE44.45
Total252.15



Intel Core Ultra 100 - Meteor Lake



As mentioned by Tomshardware, TSMC will manufacture the I/O, SoC, and GPU tiles. That means Intel will manufacture only the CPU and Foveros tiles. (Notably, Intel calls the I/O tile an 'I/O Expander,' hence the IOE moniker.)

 

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Hitman928

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But that leaves me with why are 24 cores allowed if the P-cores are turned off?


View attachment 95246

From what I remember, the lower screenshot with the boot screenshot wasn't a part of the original leak from yuuki_ans, so it could just be from a later sample where it was working or someone turning on all CPUs and trying to run it even with the hardware bugs. Just speculating though.

Edit: looked it up and the boot sequence screenshot was from a different leaker, so most likely the sample they had running was after the P-cores were fixed.
 
Jul 27, 2020
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Imagine Intel decides no more taking punches lying down and debuts ARL with 32 E-cores. BAM! just like that and then AMD is forced to use their plan B too. And there will be much rejoicing and glee all around. Here, at least. I hope.
 

dullard

Elite Member
May 21, 2001
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Edit: looked it up and the boot sequence screenshot was from a different leaker, so most likely the sample they had running was after the P-cores were fixed.
That would make sense if they were different points in time. As it was, it confused me and was quite unclear.
 

SiliconFly

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Mar 10, 2023
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Imagine Intel decides no more taking punches lying down and debuts ARL with 32 E-cores. BAM! just like that and then AMD is forced to use their plan B too. And there will be much rejoicing and glee all around. Here, at least. I hope.
I assume you're talking about ARL 8P+32E, right? Just a thought... won't a cpu with 8 P cores & 32 E cores have a very high TDP?
 

H433x0n

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Mar 15, 2023
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Imagine Intel decides no more taking punches lying down and debuts ARL with 32 E-cores. BAM! just like that and then AMD is forced to use their plan B too. And there will be much rejoicing and glee all around. Here, at least. I hope.
I’m a big fan of heterogenous architectures and they’ve worked flawlessly for me in both games and development workloads. In my experience, the ecores and their scheduling has always done as advertised.

That being said, 8P+32E is too much for me. TBH, even 8P+16E is pushing it. I’d much prefer an i9 configuration that is 8P+8E with the ecores performance being closer to parity with PCores (which it seems Skymont will achieve).
 

dullard

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May 21, 2001
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Here is an Alder Lake graph of energy consumed to complete a task:

Source: https://chipsandcheese.com/2022/01/28/alder-lakes-power-efficiency-a-complicated-picture/

Notice how the Gracemont E-cores use the least amount of energy to do the job in the 0.8 GHz to 2.0 GHz range. Yet Intel runs that chip with E-cores at 2.7 GHz base and boosts to 3.8 GHz. This burns up a ton of excess energy. Especially in turbo mode, they consume over 3X the power to do the same job as if they were at a lower frequency. Double the E cores, cut the power to each in half, and you'll get a much more efficient CPU.
 

SiliconFly

Golden Member
Mar 10, 2023
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I think Intel can manage it in 250W or so. And unlimited power mode may go up to 330W, for maybe 10% extra MT performance.
Even I guessed it may shoot above 300W. At 300W/330W, a lot of people may find it very unappealing! (myself included)

They should just stop with 8P+16E max. Thats more than sufficient I think.
 

DavidC1

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Dec 29, 2023
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That leak IS accurate.






The picture of Lunarlake from Intel's process roadmap a while back is the EXACT mini version of the picture in the Lunarlake MX leak.
 

Geddagod

Golden Member
Dec 28, 2021
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That leak IS accurate.






The picture of Lunarlake from Intel's process roadmap a while back is the EXACT mini version of the picture in the Lunarlake MX leak.
lmfao good catch
 
Jul 27, 2020
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Regarding that, here's a theory.

LNL has LP E-cores, not normal E-cores which means they will likely not participate in heavy MT tasks, just like the two LP E-cores in MTL are programmed to take a backseat in everything except watching videos or browsing.



So if the LNL LP E-cores are programmed identically, we come to a startling realization. That 1.5X MT perf increase over MTL-U is ALL LNC P-cores!!!!

I think that might be why adroc considers LNL not terribad.
 
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Abwx

Lifer
Apr 2, 2011
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I am glad you are stating it this way now, it is more clear for everyone else and will be less controversial.

With that said, MTL does catch up to Hawk Point in efficiency but not until you get to significantly higher power levels where Hawk Point plateaus much harder in performance than MTL with increasing power. I think this just shows again the difference in design approaches and how Intel will need to change up how they approach CPU design to get back to be truly competitive. Hopefully Lunar Lake shows that they understand this and are making steps in that direction.

Methink that comparing at equal perfs is the most relevant for mobile devices where usability and battery life are the key points, moreover at 15-28W.

Agree that MTL reduce the gap and can be on par at higher powers but this require being over 64W or so, wich is DT class TDP, anyway seems that its efficency evaluation is now cornered thank to more reviews.

In the last one at NBC we can see that around 40W Phoenix has about 13% better perf, wich would amount to 30-35% better efficency if perfs were to be equalized, also MTL has about the same advantage, that is 30% better perf/watt at equal perf, than a RPL based 13700H, so there s a noticeable progress at those power ranges but still not enough to catch up with the competition s N4 advantage, not counting that Hawk Point has apparently 10% better perf/watt than Phoenix.

 

bakyt115

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Nov 21, 2016
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View attachment 95263
Regarding that, here's a theory.

LNL has LP E-cores, not normal E-cores which means they will likely not participate in heavy MT tasks, just like the two LP E-cores in MTL are programmed to take a backseat in everything except watching videos or browsing.

View attachment 95264

So if the LNL LP E-cores are programmed identically, we come to a startling realization. That 1.5X MT perf increase over MTL-U is ALL LNC P-cores!!!!

I think that might be why adroc considers LNL not terribad.
I think it is doable. if 155u have 9500 in cb23. and 8 core zen3 ~ 13000 (https://www.notebookcheck.net/AMD-Ryzen-7-7736U-Processor-Benchmarks-and-Specs.684252.0.html).
if LNL will have 6 big cores with IPC increase and clock bump it can score as 8 core zen3.
 

DavidC1

Member
Dec 29, 2023
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So if the LNL LP E-cores are programmed identically, we come to a startling realization. That 1.5X MT perf increase over MTL-U is ALL LNC P-cores!!!!

I think that might be why adroc considers LNL not terribad.
Or, that's how terrible Meteorlake and Redwood Cove is at the 15W power envelope.

50% is really not a big deal when without the swanky "firmware updates" it requires a 35-40% gain just to be on par with Phoenix. So with Lunarlake which is a next generation part it can now beat AMD's last year part, yay?

Also, TSMC's process having a more "flat" curve is a contributor too. Look at the above graph, and change the 155H's line to be flatter like the AMD chip. Lose the high power gain, for 15% gain at the low power envelope.

(Actually to be more accurate it isn't just about the process. Being a product dedicated to be a power efficient chip, the curve can be made to benefit low power at the sacrifice of high end)
 
Last edited:
Mar 8, 2024
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Imagine Intel decides no more taking punches lying down and debuts ARL with 32 E-cores. BAM! just like that and then AMD is forced to use their plan B too. And there will be much rejoicing and glee all around. Here, at least. I hope.

Man, they're not "taking punches lying down", they're pummeled - almost entirely exsanguinated. If intel was capable of packaging that much in a consumer level socket, they'd have done it already... presumably with 12-16 big cores in a package like AMD does. Instead, we're trapped at 8P+++++ much like we were trapped on 14nm+++++.

Here is an Alder Lake graph of energy consumed to complete a task:
View attachment 95252
Source: https://chipsandcheese.com/2022/01/28/alder-lakes-power-efficiency-a-complicated-picture/

Notice how the Gracemont E-cores use the least amount of energy to do the job in the 0.8 GHz to 2.0 GHz range. Yet Intel runs that chip with E-cores at 2.7 GHz base and boosts to 3.8 GHz. This burns up a ton of excess energy. Especially in turbo mode, they consume over 3X the power to do the same job as if they were at a lower frequency. Double the E cores, cut the power to each in half, and you'll get a much more efficient CPU.

This would certainly lead to a more efficient CPU, but would it be a particularly useful one for something aside from a you-know-what load of almost nothing jobs? Like, my 12700F would abandon E-Cores when I shook around a window too fast... Would a small army of wet noodle cores really be preferable over a brigade of strong performers?
 

dullard

Elite Member
May 21, 2001
25,124
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This would certainly lead to a more efficient CPU, but would it be a particularly useful one for something aside from a you-know-what load of almost nothing jobs? Like, my 12700F would abandon E-Cores when I shook around a window too fast... Would a small army of wet noodle cores really be preferable over a brigade of strong performers?
The 12700F (and anything from the 12600KF to 12700K) is probably the worst possible way to have E-cores configured. Having 4 E-cores is terrible. Like really, really terrible. They are not run in a power efficient way as that graph shows. And, you are correct, in the case of the 12700F there isn't enough of the E-cores to actually do much of anything useful. Your chip has 4 power hungry wet noodles.

For Alder Lake the 12600 is the star: no E-cores. Or jump to the 12900 line: 8 E-cores. The Alder Lake chips in-between should never be purchased or used by anyone (or at least seriously consider disabling the E-cores if you must use those chips.)

That all changes when you have enough E-cores though. They have to be set to a low frequency and low power mode in order to have many E-cores in the TDP. (1) Meaning if you are doing something that doesn't need them they don't take energy and produce heat leaving the P-cores to do what they do best. (2) When you do need the E-cores, you have a large army of them to have many more cores for parallel tasks that need many threads. This stemmed from a discussion of 8P + 32E cores. That is 40 cores. Not 40 threads consisting of many hyper-threading threads that are even weaker than E-cores, but 40 cores to do parallel tasks. That can crunch numbers far better than any consumer CPU sold to date (here I am not including workstation and server CPUs or any future CPUs).
 
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eek2121

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Or, that's how terrible Meteorlake and Redwood Cove is at the 15W power envelope.

50% is really not a big deal when without the swanky "firmware updates" it requires a 35-40% gain just to be on par with Phoenix. So with Lunarlake which is a next generation part it can now beat AMD's last year part, yay?
Considering LNL is a 4+4 design, it appears to have much higher performance per clock than AMD’s design, if the leaks are accurate.
 

ondma

Platinum Member
Mar 18, 2018
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Man, they're not "taking punches lying down", they're pummeled - almost entirely exsanguinated. If intel was capable of packaging that much in a consumer level socket, they'd have done it already... presumably with 12-16 big cores in a package like AMD does. Instead, we're trapped at 8P+++++ much like we were trapped on 14nm+++++.



This would certainly lead to a more efficient CPU, but would it be a particularly useful one for something aside from a you-know-what load of almost nothing jobs? Like, my 12700F would abandon E-Cores when I shook around a window too fast... Would a small army of wet noodle cores really be preferable over a brigade of strong performers?
If it is so horrible, why did you buy it??
 

Hulk

Diamond Member
Oct 9, 1999
4,269
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Here is an Alder Lake graph of energy consumed to complete a task:
View attachment 95252
Source: https://chipsandcheese.com/2022/01/28/alder-lakes-power-efficiency-a-complicated-picture/

Notice how the Gracemont E-cores use the least amount of energy to do the job in the 0.8 GHz to 2.0 GHz range. Yet Intel runs that chip with E-cores at 2.7 GHz base and boosts to 3.8 GHz. This burns up a ton of excess energy. Especially in turbo mode, they consume over 3X the power to do the same job as if they were at a lower frequency. Double the E cores, cut the power to each in half, and you'll get a much more efficient CPU.
Am I reading this correctly?
Let's look at 2GHz.
4 Gracemont cores requires about 3000J
4 Golden Cove cores requires about 3750J
4 Skylake Cores requires about 4200J

I knew that Gracemont was area efficient but I did not know that below about 3.2GHz it is more power efficient than Golden Cove.

This chart brings some economic realities of CPU manufacturing to light. First of all, if you want incredible MT efficiency just throw a huge amount Gracemont clusters at 1.4GHz at the task. For ST 6 or 8 Golden Coves will do the job. Problem is of course that would be a huge and expensive die!

Performance/Efficiency/Cost

Pick two. You can have performance and efficiency but at higher cost. Or low cost and high efficiency but you'll also have low performance. Or you can have low cost and high performance and low cost (Raptor Lake).

The reason I put Zen 4 above Raptor Lake is because it does much better than Raptor Lake at hitting high performance, high efficiency, and low cost.
 

dullard

Elite Member
May 21, 2001
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Am I reading this correctly?
...
I knew that Gracemont was area efficient but I did not know that below about 3.2GHz it is more power efficient than Golden Cove...Pick two. You can have performance and efficiency but at higher cost. Or low cost and high efficiency but you'll also have low performance. Or you can have low cost and high performance and low cost (Raptor Lake). .
Yes, I think you read it correctly.

I think the key information is the crossover at ~3.1 GHz to ~3.5 GHz depending on the benchmark. The Gracemont E-cores can be power efficient. But Intel is having them turbo to ~3.8 GHz. That is a frequency at which the Gracemont E-cores are no longer power efficient. It isn't that they can't be power efficient, it is that they are being run in a condition that is terrible for power efficiency.

Intel had an idea for power and area efficient cores--then they shot themselves in the foot by running them at a very power inefficient frequency.

A large part of it was voltage supplied to the cores. If I recall correctly the Alder Lake E-cores get the same voltage as the P-cores. Meaning they can't readily get a good performance/efficiency combination. If you are already running the E-cores at a higher voltage than necessary (that is, you are already in a high power situation), might as well get that extra performance from them.

You can theoretically pick 3, just not with the way those chips are configured.

The remaining blame comes from motherboards, reviewers, and users suppling the chips with high power levels. Put on a massive cooler, run with motherboard settings without power limits, and you get an inefficient chip with really, really inefficient E-cores. Use a smaller cooler or set the motherboard to lower power settings and you can get closer to their efficient points (close to their base frequency under the 3 GHz crossover).
 
Jul 27, 2020
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A large part of it was voltage supplied to the cores. If I recall correctly the Alder Lake E-cores get the same voltage as the P-cores. Meaning they can't readily get a good performance/efficiency combination. If you are already running the E-cores at a higher voltage than necessary (that is, you are already in a high power situation), might as well get that extra performance from them.
E-cores not having their own dedicated voltage domain is one big clue (at least to me) that Alder Lake was hurriedly put together. MTL missing the mark and not meeting general expectations as a Zen 4 mobile killer is another strong clue that Intel never anticipated that AMD could come out with Zen 3 and then smack them right after with Zen 4. They are still trying to compose themselves after the rude slap in their faces. Lunar Lake looks promising but it's going after a different target altogether (thin, light, 20 hour battery life). If Arrow Lake isn't able to save them from the third groin kick in the form of Zen 5, oh boy!
 
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Hulk

Diamond Member
Oct 9, 1999
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Yes, I think you read it correctly.

I think the key information is the crossover at ~3.1 GHz to ~3.5 GHz depending on the benchmark. The Gracemont E-cores can be power efficient. But Intel is having them turbo to ~3.8 GHz. That is a frequency at which the Gracemont E-cores are no longer power efficient. It isn't that they can't be power efficient, it is that they are being run in a condition that is terrible for power efficiency.

Intel had an idea for power and area efficient cores--then they shot themselves in the foot by running them at a very power inefficient frequency.

A large part of it was voltage supplied to the cores. If I recall correctly the Alder Lake E-cores get the same voltage as the P-cores. Meaning they can't readily get a good performance/efficiency combination. If you are already running the E-cores at a higher voltage than necessary (that is, you are already in a high power situation), might as well get that extra performance from them.

You can theoretically pick 3, just not with the way those chips are configured.

The remaining blame comes from motherboards, reviewers, and users suppling the chips with high power levels. Put on a massive cooler, run with motherboard settings without power limits, and you get an inefficient chip with really, really inefficient E-cores. Use a smaller cooler or set the motherboard to lower power settings and you can get closer to their efficient points (close to their base frequency under the 3 GHz crossover).
You can have all three within reason but the choices are provided is an economic reality for CPU manufacturers. It is why we have hybrid CPU's.

As for the E core frequency, you can clock them where ever you want with a K chip, right?
 
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