Yeah it sounds awesome honestlyYeah I expect Kraken to be a bit smaller than PHX, but not by much. Just basically offer similar levels of MT and iGPU performance (better at lower power, worse at higher power if I were to guess) with a better NPU and ST performance. So similar price for an overall mostly improved product.
Thanks for answering. Well, since Strix Halo will be very powerful you of course would like to be able to use all that performance. Otherwise one might as well get a cheaper, and lighter laptop with less performance.But assuming the full 125W, you should expect probably a good deal less battery life than the M3 Max also with both CPU and GPU fully stressed (should be around 100W total here)... But when both devices will run less than an hour, that's not a game-changing level of battery life.
Again though, this is obviously not a realistic use case (who'd stress both the CPU and GPU of a laptop at the same time on battery?), so like, why do you even care?
The main purpose is not to game/work on battery, it's to easily move from one location to another while packing your data and enough compute power. Battery life is important when using the machine for lighter complementary tasks (like browsing, attending meetings / calls, doing code review and all other work related tasks which are time consuming and more about access to data rather than raw compute). These machines will always eat the battery in just 1 hour on performance profiles because nowadays we can easily cool 90W+ in a reasonably light chassis, so there's always 90W+ chips we can put int there. The battery life is a constant in this equation and a choice made by the user, the variable is performance or work done. If you want to evaluate battery life as a variable, then turn performance/work done into a constant.But if it’ll have a battery life of less than 1 hour at close to max load, I think that’ll be far too little for many use cases. E.g if used as a development PC compiling SW, or doing heavy gaming. It would work fine if the laptop is plugged-in to a power socket though. But then it essentially becomes a desktop / SFF PC in a laptop form factor, and not something that can be used while on the move which usually is one of the main points with a laptop.
The cheaper laptop with less performance will have lower batter life for the same workloads, assuming we're not moving all the way down to a 1/10th power target.Well, since Strix Halo will be very powerful you of course would like to be able to use all that performance. Otherwise one might as well get a cheaper, and lighter laptop with less performance.
I don't have many doubts about how great performance 'Strix Halo' will be ...
I am not worried about battery times neither ...
My main concern, I admit it ... is 'power consumption' when idle ...
My future laptop will have to be on 24x7 ... ... it will ocasionally be very highly demanded ... very ocasionally. It seems 'Strix Point' is more fit for the bill ... then it was stated around here that 'Strix Halo' would come on N3E manufacturing node ... which was good news for my future use case ...
I want 'Halo' ... but common sense is telling me ... 'Strix Point' ...
For development work when on the move, I usually go for a high quality light laptop (~1 kg) which is easier to carry around and travel with. Then I set up a remote session from the laptop to my desktop PC to perform heavy workloads such as compiling SW for X hours.The cheaper laptop with less performance will have lower batter life for the same workloads, assuming we're not moving all the way down to a 1/10th power target.
Zen 3 or Zen 3+?So long as a put my zen3 on power saving mode ( Lenovo slim 5 pro) I can go a solid 10-12 hours in proper productivity workloads , did it yesterday infact.
Or they managed the same A : P, and 100% uplift confirmed!AMD have reduced the area : perf ratio targets
You can go by transistor count.What is interesting about that is it suggests the Zen 5 CCD is 90mm which is around 29% larger than the 70mm Zen 4 CCD. That is a larger jump than Zen 2 to Zen 3 which was about a 14% increase in area.
If people are thinking Zen 5 is going to offer a Zen 3 like performance uplift then it would mean AMD have reduced the area : perf ratio targets (or Zen 3 massively over delivered on them)
I think your math is a bit off. If Zen4 core is 2.83mm^2 then the L2+L3 area (and interconnect) is around 49mm^2 (Zen4 CCD is 70-72 mm^2). If L2+L3 area stays the same (But I estimate a 3-4% reduction) then the core area for Zen5 should be greater than 5mm^2 (my guess would be 5.3mm^2). At a 6% density improvement going from N5 to N4(P) we would have almost a doubling of transistors per core...You can go by transistor count.
Zen 4 CCD has 6500 MTr compared to Zen 3 with 4150 MTr.
Zen 4 Core@2.84mm2 has around ~330MTr compared to Zen 3@3.3mm2 with < 200MTr (Without L2 in either case)
Zen 4 Core w/o L2 has 70%+ more MTr than Zen3.
If we are talking about keeping L2 and L3 at similar capacity, and the GMI/JTAG/DBG unchanged, that is >50% increase in core area for Zen 5 when process is not offering increased density. (Probably there will be some small density gain ~2% to ~3%)
This is a massive increase in MTr per core but lesser than Zen 4 over Zen 3.
Also not clear if the CCD size includes scribe lines or not. Zen 4 is 66mm2 without scribe lines.
I think your math is a bit off. If Zen4 is 2.83mm^2 then the L2+L3 area (and interconnect) is around 49mm^2 (Zen4 CCD is 70-72 mm^2). If L2+L3 area stays the same (But I estimate a 3-4% reduction) then the core area for Zen5 should be greater than 5mm^2 (my guess would be 5.3mm^2). At a 6% density improvement going from N5 to N4(P) we would have almost a doubling of transistors per core...
You can easily confirm this because the CCD size, if we consider the cache area being the same, is due completely to core size increase, that is, 90-72=18mm^2, that is 2.25 mm^2 of core size INCREASE, per core.
Why are you INCREASING the cache area for Zen5? It should DECREASE. And why using 2% for density increase when TSMC states 6% for everything (so logic should be even higher)? Again, if you consider that as L2+L3 cache is the same in Zen5, we have at least 82-66 (16) mm^2 increase of die size due to Zen5 core improvements alone.View attachment 97072
The math is not precise indeed but for the Zen 5 CCD size of ~90mm, the actual die would be around ~82 mm2.
I added some increase in L2 and L3 due to the updated prefetchers
Zen 4 CCD is 66mm2 and CCX is 55mm2 official values from ISSCC
View attachment 97069View attachment 97070
Just 5800HZen 3 or Zen 3+?
The 6000s had a pretty amazing balance/power consumption.
You can go by transistor count.
Zen 4 CCD has 6500 MTr compared to Zen 3 with 4150 MTr.
Zen 4 Core@2.84mm2 has around ~330MTr compared to Zen 3@3.3mm2 with < 200MTr (Without L2 in either case)
Zen 4 Core w/o L2 has 70%+ more MTr than Zen3.
If we are talking about keeping L2 and L3 at similar capacity, and the GMI/JTAG/DBG unchanged, that is >50% increase in core area for Zen 5 when process is not offering increased density. (Probably there will be some small density gain ~2% to ~3%)
This is a massive increase in MTr per core but lesser than Zen 4 over Zen 3.
Also not clear if the CCD size includes scribe lines or not. Zen 4 is 66mm2 without scribe lines.
A sizeable part of the inflated transistor count in Zen 4 was dedicated to frequency uplift, so the numbers between Zen 4 and Zen 5 are not comparable to the Zen 3 to 4 transition.
Including the logics density improvement of N4 over N5 this amount to 37% bigger effective area, now if the caches and some other circuitries are comparable to Zen 4 then this is a hint that Zen 5 core is much bigger than just +37% transistors count wise.
I don't think that matters too much because spending transistors for clockspeed or spending them for IPC all nets out to spending transistors to increase performance.
Just wonder what can be expected from Strix Halo vs 9950X? Some predictions below based on what has been communicated so far:
Interesting! Why would Strix Halo win all bandwidth bound tasks.Lots of variables. Halo obviously wins all bandwidth bound tasks. Monolithic improves latency but otoh the whole memory subsystem is likely geared towards bandwidth at the expense of latency.
I'm assuming Halo is 8 Zen5 + 8 Zen5c, so in that case 9950X obviously wins all embarrassingly parallel tasks that respond well to frequency if you provide enough juice.
The big question for Halo whether it's single or dual CCX (lots of talk that 16 core Zen5c is now single CCX, so Halo also could be), and the amount of L3 per CCX.
Just FYI but Strix Halo isn't monolithic. It's using chiplets + advanced packaging (akin to Navi 31 or MI300 or future Zen 6).+Monolithic die, so lower idle power consumption.