Whatever the solution is, it will certainly involve cycling threads between CPUs, such that any threads which are holding back dependents will move to big cores. That will incur a penalty, but the efficiency gain with small cores, and the resulting TDP headroom afforded to the big cores, is...
It reads more like a zen based processor with a small cluster of 2-4 arm style cores that can take up small tasks, rather than an actual big.little processor. But a layout where each zen core contains a small co-processor might work as well.
This is the first data we've seen for the 10SF process using more power. It seems it scales well and can clock high. I would expect Intel to keep the single thread crown w/r/t alder lake vs. Ryzen 6xxxx.
I doubt it's that. They seemed more difficult to fix than that, and I think AMD would have promoted the fact if they did manage to fix that so quickly.
Meanwhile genoa is expected to offer 96 cores, 12 channels of DDR5 (which should help to offset lack of HBM) with a 10% lower TDP. It seems 2022 will only increase the server gap between Intel and AMD.
Being fabbed on 10SF, which should be comparable to TSMC 7nm in density and efficiency, I think the Icelake Xeon review makes it pretty clear that Intel's newest cores are simply less efficient than current Zen. Tigerlake cores wouldn't change the equation much there.
The benefits of big.little are more apparent on laptops, where there will be a very real increase in battery life. But there should be benefits on desktop too. Hypothetically, if you just wanted to maximize multicore performance on desktop, you would ONLY use little cores. They're more...
Optimizing homogenous multicore performance would likely require moving threads from little to big cores periodically if keeping time is important for the program. That would entail a performance hit whether or not the scheduler is smart enough to do it (either cores will be waiting, or there...
Does anyone have an idea about what percentage of multicore workloads will scale properly with assymetrical cores? I know some programs divide a workload evenly between cores but need to wait for all threads to finish before moving forward. Might this be a common problem for Alderlake?
Density did NOT go up for the 14nm pluses. They actually relaxed density slightly to boost clock speeds. The reason for the good scaling is the parts of the die which didn't double, such as memory controller, gpu, etc.
I agree with you about the CPU, but with a reduction in resolution comes a reduction in memory consumption from graphics (RAM is combined for CPU and GPU). They just need it to approximately scale so the CPU has equal resources.
It could also be salvaged Series X SOCs which have defective memory controllers and/or CUs. Or a combination of salvaged and custom cut down chips. I'm guessing this is the case because the Series X SOC has other additions (texture compression being one) which the S will need to match for...
One of the reasons AMD went monolithic for the APU is power consumption for notebooks. The chiplet design has a power consumption disadvantage for I/O, it's not enough to really impact desktops but will definitely hurt battery life in thin and light laptops. Laptops are the most important...
We don't know. The most likely answer is it's just a matter of priority, maybe sales of last gen desktop APUs were low, or the profit margins weren't as high as in laptops.
TSMC is projecting mass production of 5nm in 2H2020, while Intel is here stating Q42021 for their (nearly equivalent) 7nm. TSMC's lead should only increase beyond one year with 3nm.
I think, for the first time in my life, I have the confidence to short sell a stock. This discussion here, and the reality of what Intel will likely have for sale by the end of 2021, while TSMC will be solidifying its 5nm lineup and getting 3nm ready, makes it clear.
As one poster said, tensor cores are invaluable, but RTX cores are not as necessary for their job (about twice as good as shaders). Vega can already perform raytracing fairly well, and that's because the unified shaders are optimized for compute in some ways. The performance uplift tensor...
How is it a childish game? It's not necessarily intentional, it's just there on the package design that there's room for another chiplet. It makes sense from a design perspective to make room for two chiplets from the beginning. This way they won't need to change a thing when a 12/16 core...
The primary benefit of using the 8 core chiplets is avoiding another mask, but the smaller IO die requires another mask anyways. They could design a monolithic 12 core chip anyways, which would simplify manufacturing and lower costs for AMD. If they want to jump straight to 16 cores, then they...
There are two serious issues with the update.
1) The right side bars (trending threads and ask the community) force all text into a central column, and create empty space the whole way down. Move these bars to the left side under the contents, and we only lose one side.
2) There is no way...
The system clearly works for GPUs, which are even larger and more energy intensive. And bandwidth, with PCIe4 and eventually 5, will start to become sufficient even for CPUs. I could see the card system being shared by both GPUs and CPUs for server farms which are going for density.
If you...
Actually in both consoles one (or was it two?) of the cores are reserved for the OS anyways. And you also can't expect developers to be able to perfectly thread out a game, there will be limiting factors. Nevertheless, 6 core cpus do have advantages over 4 these days. I think it's in line...
In the past, with the Q6600 for example, processor steppings allowed higher clock frequencies with no changes to the process node. Coffee lake refresh could be the same.
You can't just interpolate linearly though. Lower frequencies require linearly lower power, but also run at a lower voltage, regardless of core count, which scales with the square. So speeds would end up somewhat higher. This is one of the core benefits of multicore processors in the first place.
It seems I have. I've cleared CMOS, tried the built in bios recovery, resetting the EC, nothing worked.
I did try an external display, no signal output, nice idea though.
I spent some time editing IFR values of the BIOS using UEFI shell, and successfully made some changes until, unfortunately, one particular change (GPU memory aperture size) bricked the laptop completely. Nothing can be displayed on the laptop, it cannot boot into bios recovery mode, and all...
I wouldn't expect it to help more than 1-200Mhz. The process technology AMD used just doen't go that high, it's for low power, which allows them to run more cores but more slowly. Also the only way it would help is if through trial and error you disabled just the cores which are holding back...
No there were changes to Kabylake that made video decoding more energy efficient. Also Kabylake-R has updated video output (HDMI 2.2 iirc). Since the i3 KL-R has this as well it's probably a salvaged die.
It's not die size but power efficiency that matters most. Simply scaling up the IGP, which isn't nearly as simple as you think, wouldn't give a very efficient chip, and wouldn't fit in the required TDP.
This should definitely be lower power than having a discrete GPU because shorter interconnects (even if they are PCIe) will consume less power, as will HBM, which isn't currently found in laptop GPUs.
It seems Intel passed up the opportunity to use HBM as an L4 cache for the processor. This...
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