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  1. N

    Discussion Apple Silicon SoC thread

    What evidence do we have for this (increased L1 latency)? BTW if the pipeline grows longer, that will NOT show up in "per instruction" latencies, only in branch misprediction cost (which is EXTREMELY difficult to measure correctly on an Apple-level chip, I haven't seen any good analyses). If...
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    Discussion Apple Silicon SoC thread

    I think SOMETHING like that occurred but (controversial claim), different ordering, and so there was a falling out between ARM and Apple over details. If we look at SVE, the spec seems to have, uh, a troubled history. SVE, various obvious problems so SVE2, then a constant stream of minor...
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    Discussion Apple Silicon SoC thread

    My finances do not allow me to buy every shiny new Apple device that appears :). And I'm leaving the low level testing game to younger folk. I have other projects I need to work on. My hope is that over the next few years at least a few such people will take up the challenge. All the students...
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    Discussion Apple Silicon SoC thread

    There are two ways to push frequency higher. Run the individual transistors faster, or cut the pipeline into more stages that can each run faster because they do less sequential work in each stage. My GUESS (given the power numbers) is that Apple has been concentrating on the second rather...
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    Discussion Apple Silicon SoC thread

    Supposedly TSMC has Arrow Lake GPU commitments to Intel using N3B. So in terms of that, I assume it will persist. (And Intel is probably not agile enough to easily move to N3E the way Apple can, especially since they NEED Arrow Lake to ship on schedule, otherwise their whole "4 Processes in 5...
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    Discussion Apple Silicon SoC thread

    I understand the logic that SME might be present because of the header discovery. I don't fully understand the logic that it's speeding up Object Discovery. Here's my issue: how does Object Discovery execute its neural nets? I THOUGHT that GB6 CPU, deliberately, executes all such code (and...
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    Question Geekbench 6 released and calibrated against Core i7-12700

    Uhh, wot? So your contention is that most people were buying GB5 to engage in dick-measuring, and are upset that it's now targeted at useful information rather than dick-measuring? OK...
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    Discussion Apple Silicon SoC thread

    Here's a nicer (or at least richer context) version of the same GB5 result: https://browser.geekbench.com/v5/cpu/compare/19959697?baseline=19960927
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    Discussion Apple Silicon SoC thread

    You might want to add Jetstream2 to your list... If we believe preliminary numbers, there has been a MASSIVE improvement in JS performance...
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    Discussion Intel current and future Lakes & Rapids thread

    You can for Wolfram (company that makes Mathematica). Their design meetings are open and available on YouTube and have been for at least five years or more. Mathematica probably has the best bugs to complexity ratio of any software on earth (at least that I know of; maybe avionics is better –...
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    Question Alder Lake - Official Thread

    That's a wrong (or at least extremely limited) presumption. You can compare the two on git: https://github.com/videolan/x265/tree/master/source/common/aarch64 https://github.com/videolan/x265/tree/master/source/common/arm vs https://github.com/videolan/x265/tree/master/source/common/x86 Unless...
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    Discussion Apple Silicon SoC thread

    Test. Are article comments down? --- Well forum is working. I guess we wait and see if they are fixed tomorrow.
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    Discussion Microarchitecture Comparison Chart

    The basic numbers are nice to have, but as I keep saying even more important are the ALGORITHMS used by the CPU. What are the branch prediction algorithms, the cache replacement algorithms. Something as basic is: is a cache maintained of structures encountered during a page walk, and if so of...
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    News Ampere Altra Launched with 80 Arm Cores for the Cloud（Performance Estimates）

    (a) You assume people read these threads in a particular order and so know what others have said in reply. That's a bad assumption. There are many ways that you land up thrown into the middle of a thread. One common one is looking at one's comments that were replied to. Another is starting at...
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    News Ampere Altra Launched with 80 Arm Cores for the Cloud（Performance Estimates）

    Just as a future hint — it doesn’t come across as very impressive when your complaint that someone has hijacked a thread gets the topic of the thread wrong... The CPU is called Altra not Altera. I’ll ignore the fact that you clearly didn’t understand my comment, since one thing the internet...
  16. N

    News Ampere Altra Launched with 80 Arm Cores for the Cloud（Performance Estimates）

    What are you talking about??? No "SVE2 is locked-up behind ARMv9" exists anywhere except in your imagination. SVE and SVE2 are part of ARMv8, have been since the day they were announced.
  17. N

    News Ampere Altra Launched with 80 Arm Cores for the Cloud（Performance Estimates）

    We now know a *lot* more than a few days ago: and the whole successor threads
  18. N

    News Ampere Altra Launched with 80 Arm Cores for the Cloud（Performance Estimates）

    I'd put it differently. People talk about diversity in CPUs as though that's some sort of wonderful flower that everybody wants -- OEMs want to support 5 different CPUs, customers want to own seven different OS's running on 8 different cores. Utter nonsense! Diversity is a massive expensive...
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    Discussion Apple Silicon SoC thread

    Yes, $40 for A14 (just the SoC, not including the DRAM also on the package) matches other iPhone BOM estimates.
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    News Ampere Altra Launched with 80 Arm Cores for the Cloud（Performance Estimates）

    What EXACTLY are you wondering about? There is no ARM 256bit SIMD. There is SVE/2, and you don't have to wonder about it, there's plenty of documentation available on the internet...
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    News Ampere Altra Launched with 80 Arm Cores for the Cloud（Performance Estimates）

    Please, for the love of god, stop talking about "128bit simd" like that is some sort of monolithic thing across all ARM. There is ZERO reason why multiple SIMD units implemented on a very wide machine should perform any worse than fewer wider SIMD units, and this is in fact exactly what we see...
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    News Ampere Altra Launched with 80 Arm Cores for the Cloud（Performance Estimates）

    The reason for "bothering" is an expectation that ARM will get faster more rapidly than AMD. Which means that the large companies that aren't Amazon (and Apple?...?), if they have any sense, will be buying a few today to start preparing for their large scale transitions over the next few years.
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    Discussion Speculation: The Rise of RISC-V

    No. If you rely on a BS benchmark, which you then cannot even calculate close to correctly you have UTTERLY squandered your credibility. (As have EE Times, not that they had much to begin with.) Next question.
  24. N

    Discussion Apple Silicon SoC thread

    No it is not! It has to do with the ordering of stores. Suppose I have a CPU that executes code store rA to addrA store rB to addrB These instructions can be executed out of order depending on the order in which their operands rA, rB, addrA, addrB become available. But effective execution on...
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    Discussion Apple Silicon SoC thread

    The very fact that you can say such a thing "If it's doing work, it should be counted!" shows how UTTERLY clueless you are. Quick question. How many CPUs do you think exist on an M1? 8? 15? 50? The same is somewhat true (though less extreme) for an Intel chip. No-one bothers counting how many M0...
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    Discussion Apple Silicon SoC thread

    Well this is the difference between people whose goal is to understand technology and people whose goal isredacted Inappropriate language for the tech forums. esquared Anandtech Forum Director
  27. N

    Discussion Apple Silicon SoC thread

    Apple is comfortable with training on their devices right now... https://blog.tensorflow.org/2020/11/accelerating-tensorflow-performance-on-mac.html Sure it's not at nV hundreds of watts level - yet... It is likely that at least some of the training is being done using AMX on the CPU, and this...
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    Discussion Apple Silicon SoC thread

    This (no "uarch improvements") is far from true. Improvements in this vein include - special casing 0s and +-1s in the MAC's - support for narrower than 8-bit weights - exactly how you structure your "cache" system (ie how often you have to reload weights, and how computed can flow back into the...
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    Discussion Apple Silicon SoC thread

    I think we're going to see, over time, some fascinating changes here. NPU, GPU, ISP, even media encoder, all, from the thousand foot level, perform the same sort of thing --- many many MANY small engines all operating in parallel on (hopefully) independent pieces of data. How valuable will it...
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    Discussion Apple Silicon SoC thread

    Maybe you are not a native English speaker? Or even from a different English speaking community within the US? Cheap is a somewhat ambiguous English word. People think it means "low price" but it really means something like "low quality"; since low price and low quality usually go together you...
  31. N

    Discussion Apple Silicon SoC thread

    Apple have retained the cases of devices across every major transition for the past 20 years or so. Not just PPC to Intel, but also things like the A7 (64-bit) iPhone transition. Doing this is not a random choice, it's done for good, deep reasons. I've discussed the tech side of this elsewhere...
  32. N

    Discussion Apple Silicon SoC thread

    What is your counter argument? I agree (for multiple reasons) that a public low-price model NEXT YEAR is unlikely; but sent and I are not insisting on next year, we are saying this will be the pattern "soon" (say before 2025). The argument is that Apple has done this for every other product...
  33. N

    Discussion Apple Silicon SoC thread

    That's not the real issue. The real issue is that it shows the cost structure. One can no longer argue that "Apple could never drop these things below $800 because the BOM exceeds that". What sent and I are saying is that the BOM (TODAY, and certainly in a year!) allows a price of $700 with...
  34. N

    Discussion Apple Silicon SoC thread

    TSMC started N5P testing/Risk production in 2Q2020. Meaning that (and now that I think about it, it is so obvious!) the M1X will be on N5P! THAT is what's determining its schedule. There is a precedent. Remember that the A10 came out in Sept 2016, on 16nm. But the A10X came out in June 2017 on...
  35. N

    Discussion Apple Silicon SoC thread

    Or M3... Zen to Zen2 was ~2.5 years. Zen2 to Zen3 was ~1.5 years There MIGHT be a Zen3+ competing against the A15, but I'd expect for most of its lifetime, except perhaps for a few months, Zen4 will be competing against A16.
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    Discussion Apple Silicon SoC thread

  37. N

    Discussion Apple Silicon SoC thread

  38. N

    Discussion Apple Silicon SoC thread

    I think it's always good for people to be reminded that others use their computers in very different ways. Some people care about video games, some care about FCP editing. Some care about XCode, and some about Mathematica...
  39. N

    Discussion Apple Silicon SoC thread

    Oh come on! For some people it is compiling. For some people it is various types of engineering. For me it's running Mathematica. Yes, we all know most people will be comfortable with the low end -- that's why the low end sells best! But that doesn't change the fact that there are some people...
  40. N

    Discussion Apple Silicon SoC thread

    It's 4+4 and 8+4. 8+4 makes sense; 8x4 means ???
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