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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    16GB is the lowest you can go and still populate the entire interface using chips that are still in mass production. So that's a lower bound. Recently, someone noticed a bunch of shipping manifests for Strix Halo testing boards, some of which had 32GB and others had 64GB. 128 is also possible...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Yes. They clock at core clock and the highest 1T boost of the non-x3d is notably higher.
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    News AMD 1Q2024 Earnings

    I don't actually think that's true, it's just that the segments of the server market they are still holding are the ones with the lowest ASP. At this point, AMD is basically dominating hyperscaler sales. If you are purchasing mainly the highest-end chips, and are doing so by the truckload, you...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Do you already know the naming of the cards? How is the stack split? I would assume there would be two cuts of each die, and that would work fairly nicely with 800/700 and 600/500. If the leaked specs are right, I would expect it to always beat a 7800XT, and even if it didn't, AMD has launched...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    I'm honestly more than a bit skeptical of this. Because of batching, centralized inference is much more efficient and cost-effective than inference on the edge. The total amount of hardware needed to do a lot of inference is substantially (at least 10x, probably a lot more) less when the...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Consoles historically sold most of their units in the latter half of their lifecycle, after the chips were shrunk and the console cost-reduced to (typically) less than half of the launch price. Of those 160M units that PS2 moved, about a third were the original console at close to the launch...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Probably greater. They already have a working split AVX512 implementation, it would make a lot of sense to use that for the c part.
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    The cats were built by a tiny team, that managed to massively outpetform expectations. The reason cat core development ended was not about the market, it was that someone (iirc Samsung? Not sure and I don't have time to check it) poached the entire team whole from AMD. This was before the Zen...
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    Question Is it actually true that AMD is actually publicly valued at over 3X what Intel is??

    The market cap of AMD is a bit less than twice that of Intel, not 3.5 times (258B vs 134B). Market values are never about today, they are what people expect to happen in the future. People expect that Intel will continue to lose market share, and that the problems they face in the future are...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Only way that makes sense to me is if it uses some new kind of packaging that's not compatible with any existing dies. I am skeptical.
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    Discussion RDNA4 + CDNA3 Architectures Thread

    They are not available for when the first cards launch. I would expect Blackwell release to mirror Ada in that the initial launch just has the high-end chips.
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    Discussion RDNA4 + CDNA3 Architectures Thread

    AMD/ATi was the driving force behind a lot of the earlier GDDR standards, they co-operated with a memory manufacturer to develop both GDDR3 and GDDR5. They have benefited a lot from this in the past, RV770 wouldn't have been such a success if they had not been able to ship a card with a 256b bus...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    There is no reason to make ES chips clock high. You can do the testing you need at low clocks, and just setting clocks low means you don't have to deal with binning for clocks, you can just take any chip off the line that passes functional testing and use it. It also helps hide real performance...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    I would like to note that the lower IPC score has 8GB of ram. Probably this means that the memory interface is not fully populated. I have no idea how this impacts geekbench scores.
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    By AMD's current naming scheme, any mobile products released this year should be the 8000 series. So of course they will be the 9000 series, lol. (I have no clue what they will actually be.)
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    Discussion RDNA4 + CDNA3 Architectures Thread

    What's the source on that? It would be a bit shocking to me for that to be true, GDDR7 is PAM3 and significantly different from GDDR6, a GDDR6-only memory controller would be much simpler and smaller.
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Cache bandwidth is mostly irrelevant for client inference. Caching helps when you can batch requests, but for a client inference setup you mostly just can't usefully do that. A single inference job needs to touch gigabytes of parameters, the actual usable bandwidth is just how much is left of...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Zen2 and Zen3 are both "6 wide", but 6 "what" wide differs. Zen6 is 6 uop wide, that is, in the frontend the incoming x86 ops get split into uops and at most 6 of them are submitted forward per clock. Zen3 is 6 macro-op wide, where each x86 op generally converts into one macro-op. This is...
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    Info LPDDR6 @ Q3-2024: Mother of All CPU Upgrades

    I would caution you to be a little more careful about believing in Samsung announcements. They have previously announced a whole bunch of memory products that simply never shipped in volume. I will believe that Samsung has a LPDDR5X module that can do 10.7Tbps when they actually have the chips...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    Two big reasons: Firstly, the cost of widening variable width decode is not linear, but exponential. This is the one big advantage that 64-bit ARM has on x86, they can just decide how wide they want their decode to be and duplicate the units, x86 has to deal with first finding out where the...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    I'd like to note that trying to divine AMD intentions from the product line is a bit fraught because the same rumors that led us to believe that big RDNA4 was cancelled made pains to point out that this lineup was not what AMD chose to do, it was what they were forced into by external...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    High-end chips generally take more than 4 years to design and manufacture, starting from scratch. If they intend to have a new console with bleeding-edge tech out in 2028, the project had to start last year at the latest. N7 -> N4P. I think the "oversized bus" makes sense because it uses...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    It's a thing AMD marketing likes to talk about. I'll bet you that it will be up on the slides again when RDNA4 launches. It might not be real, but it's something that will be mentioned, and it would probably match up well with the number on that leak, which is why people think that's what the...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    It's more complex and depends on cache hit rate. IIRC something like ram bw + min (1/(cache miss rate) * ram bw, ∞cache bw). It's supposed to model how much traditional ram bw you'd need to match the combination of ∞cache and ram bus. I think it was in the slides when AMD first released the...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Tbh even if the chip is capable of that, I'd fully expect AMD to juice the XT model to the very limit. Then turning on the eco mode is lef for the user.
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Assuming 32 wgp, 50TF is ~3.06GHz.
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    You seem very confused. nVidia 40 series did not use N4P for the very simple reason that they entered production nearly a year before N4P was available. They used 4N, which was one of the early 5nm processes, and not anywhere near the most advanced 5nm silicon. 4NP was developed later, using...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    If the perf rumors (<7900XTX, >7900GRE) are true, the only way this happens is if nVidia really disappoints with 5070.
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    Info LPDDR6 @ Q3-2024: Mother of All CPU Upgrades

    LPDDR is strictly point-to-point, and after a point stacking more dies in a package gets more expensive than just having a wider bus. I don't think it would be cost-effective to have 64b LPDDR6 bus for APUs.
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    Discussion Leading Edge Foundry Node advances (TSMC, Samsung Foundry, Intel)

    Note that the frequency of a single transistor* is not the same thing as the frequency of a chip using those transistors. The silicon transistors used to build modern chips are already roughly in the ~100GHz speed class if you measure just the time it takes for a single transistor to switch. But...
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Not really. Radiative cooling gets really important as things get much hotter, because the rate it happens is proportional to T⁴. Near NTP it usually does not have much of an impact, but numbers go up quickly in quartic equations.
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    How? The highest density I see is that Samsung and Micron both have 128Gbit x32 chips, those are good for up to 128GB on 256b. Am I missing something?
  33. T

    Discussion RDNA4 + CDNA3 Architectures Thread

    This is true for radiative cooling. It's completely irrelevant when you have fans that are pushing meaningful airflow.
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    Discussion RDNA4 + CDNA3 Architectures Thread

    If they only have 2 dies, I would expect them to be binned/disabled so that they have at least a x800, x700 and a x600. x900 might be a stretch, depending on how fast the top part is, but AMD has shipped generations where the same "hundred" of next gen is worse than the previous gen, see...
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    (edit: internet connection weirdness, sorry)
  36. T

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    I think Dolphin does too.
  37. T

    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    16x PCIe 5.0 is only 63GB/s. That gets you less than halfway back from 128-bit to 256-bit, and gets you all the headaches of a split bus. I wouldn't buy it, just get a mini PC with a soldered Strix Halo and fast ram on board.
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    That's up to system integrators. Search your heart and you will know the answer. (of course they will) At least it's not really possible to go below 32GB while using the most commonly produced chips.
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    Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

    It can't be fit on AM5 because it has a 256bit bus. I think that would be pointless compared to normal Strix. You are not going to eke out all that much GPU performance from 128-bit DDR5, no matter how much compute power you have on the system. (edit: should have refreshed)
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    Discussion RDNA4 + CDNA3 Architectures Thread

    Have there been any more recent info on what ram is used? 24Gbps GDDR6 seems still to be a paper product ("sampling"), while the only rumors about GDDR7 shipping seem to be for nV. It might just be 256bit 20Gbps GDDR6 again. It would be cheap, apparently most GDDR6 reaches that nowadays, to...
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