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  1. Discussion Speculation: Zen 4 (EPYC 4 "Genoa", Ryzen 7000, etc.)

    humm... Zen4 L3 bandwidth is ~50% higher, userbenchmark sees a ~50% increase :smirk:

  2. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    At this point, i doubt the extra cost is more than $15, this is an old tech for AMD... they could easily made each chiplet larger, say 128-bit bus, the complexity would be halved, and would still had a good flexibility If anything, the tiny size of the chiplet means the savings of a yield...

  3. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    another interesting thing about these MCDs, is that AMD may reuse them for FGPAs

  4. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    What are the odds of something crazy like LPDDR5x? RDNA2 was surprising with its small bus. RDNA3 is rumored to have even bigger IF, more compression and clocks over 3GHz.... bandwidth shoundt be a problem, but latency might... a cheap, low latency and power efficient memory, might be good...

  5. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Keep in mind, from the other patents: dual vector and super simd, both relie on auxiliar caches near the registry files

  6. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Indeed, just the patent have weird ways to explain it... "a CU surrounded by L0s"

  7. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    UNIFORM CACHE SYSTEM FOR FAST DATA ACCESS https://www.freepatentsonline.com/y2022/0188232.html Someone at twitter found this patent some time ago, only now looking again at @Kepler_L2 diagram of RDNA3, i think i understood... Each SIMD will have it's own L0 cache, if a miss, it will look at...

  8. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Pure expeculation: for next generation, AMD might improve the "dual vector issue" to be more flexible... Like 4 lanes of SIMD16, for a "quad vector issue"...do 1 wave 64, 2 wave32 and 4 wave16 per clock... Maybe even do unussual issues like wave48 + wave16

  9. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    It's a follow up of the patent "super-simd", RDNA3 can (aparently) chain mutiple instructions in theyr dual ALUs, pretty much bouncing the results of one alu to another... it's nothing alike the old gpus This last patent descibes that a compiler keeps track of any dependencys, and if it finds...

  10. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Vliw compiler is back... but more advanced https://www.freepatentsonline.com/y2022/0188120.html

  11. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    I really can't remember another gpu that can do a wave64 in a single clock, very impressive.

  12. Question AMD Phoenix/Zen 4 APU Speculation and Discussion

    not a pro at this, but will do my best It alleviates one of the most important GPUs bottleneck: register file... (a major bottlenck of GCN gpus) doing a wave64 in 2 clocks means twice the time it needs to hold data... Problem shows up when the gpu needs to execute a critical wavefront, but the...

  13. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Whats your theory on the double wavefront? Just saw at twitter an interesting speculation: the gpu launches 2 wave32 at the same time, emulating as 1 wave64... this would allow the gpu to launch 1 wave64 per clock

  14. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Nope, a wavefront will use as many shaders it can... I can see 2 uses of it: 1- Similar to hypertreading in CPUs, a way to use all resources avaible when possible. The drivers would need to be aware of it, will have diminushing returns If devs fine tune for it; 2- to Double the shaders...

  15. Discussion RDNA 2 6nm Refresh

    There was any talk about EUV improving Fmax?

  16. Question [AT] AMD amended WSA with GloFo

    Xilling still sells alot of FPGAs on older nodes, even 28nm ones Also, GPU I/O dies could be produced at glofo

  17. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    GFX11?... interesting! Do we have any leak/patent of chages? ...i mean, other than MCM

  18. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    No, look at the PS5... is uses less power than a 5700xt while having higher clocks and a 8 cores cpu... without infinity cache

  19. Question Speculation: RDNA3 + CDNA2 Architectures Thread

    Theoricaly the 6900xt is 2,6 times faster than the 5700xt from a pure Gflop persperctive, never mind the changes at ROPs, geometry and efective bandwidth... yet at 4K resolution is baraly 1.8 times faster Diminishing gains is gonna hit even harder past 80CUs, so does clocks speed, Infinity...

  20. Question DLSS interaction with Global Illumination

    Maybe at lower resolution the engine shoot less rays... less bounce, less ilumination

  21. Question Speculation: RDNA2 + CDNA Architectures thread

    Drivers is also a good guess on bad RT performance, XBOX SXS is faster than the 6800XT at Minecraft RTX

  22. AMD 6000 reviews thread

    4k is a cursed resolution... Ampere doubled FP32, massive bandwidth... not very impressive results rdna2 doubled everything, plus 0.5Ghz on top... reee.. even worse

  23. Design changes in Zen 3 (CPU/core/chiplet only)

    New chiplet is 80.7mm2. A small increase for such massive gains... Source is Semiaccurate and Toms hardware

  24. Question Speculation: RDNA2 + CDNA Architectures thread

    You nailed it...

  25. Question Speculation: RDNA2 + CDNA Architectures thread

    This just hit me: IF Microsoft super resolution is real, infinity cache is gonna have even higher hit rates... At internal rendering of 1080p, the hit rates must be over 80%

  26. Question Speculation: RDNA2 + CDNA Architectures thread

    Since the confirmation of the Infinity cache, i am wondering, what the L2 cache is used for? Infinity and L2 cache seem to fit the same role...

  27. Question Speculation: RDNA2 + CDNA Architectures thread

    I won't be surprised if someone creditable says this is a good trade of... SRAM is known to be easy to yield

  28. Question Speculation: RDNA2 + CDNA Architectures thread

    It is nuts! But the alternarives are worse. A 384-bit bus already is ~96mm2, at very high defect sensity... way more than SRAM... HBM2 is costly, a gddr6x seems like a stretch (insane hot, palm4)

  29. Question Speculation: RDNA2 + CDNA Architectures thread

    Well, it's possible that big Navi is using SOiC from TSMC, and the Infinity cache is indeed a off chip Anyway a high end gpu with only 256 bus is kinda nuts already... there is a non-trivial economic impact of the board complexity/cost... it gets more interesting at 5nm, when SRAM shrink 30%...

  30. Question Speculation: RDNA2 + CDNA Architectures thread

    Proof Link for the infidels... https://lists.freedesktop.org/archives/amd-gfx/2020-October/055007.html

  31. Discussion AMD Cezanne/Zen 3 APU Speculation and Discussion

    An interesting review would measure the Igp performance by the bandwidth savings of the cpu cache...

  32. ***OFFICIAL*** Ryzen 5000 / Zen 3 Launch Thread REVIEWS BEGIN PAGE 39

    Good point, didn't thought about it... Cezanne is likely intended to ship with a Dgpu... while Van Gogh is intended for ultra low power... Mmm... maybe zen3 is not as efficient as zen2 at lower clocks... hence the lower base clocks of zen3, while Van Gogh and consoles use zen2

  33. Question Speculation: RDNA2 + CDNA Architectures thread

    It's not that easy as CPUs, The terabytes of data crossing to each chiplet would require some "big" xGMI controlers, 8 compute gpu chiplet is probably gonna reach diminushing returns While a MCM Navi10 of only 2 chips, both would be ~150mm2 (i added some redundancy)... Even the big navi, the...

  34. Question Speculation: RDNA2 + CDNA Architectures thread

    I really doubt any future gpu chiplet is gonna split the compute units... similar to zen2, a IO die and another compute die

  35. ***OFFICIAL*** Ryzen 5000 / Zen 3 Launch Thread REVIEWS BEGIN PAGE 39

    It's very frustrating, Cezanne and Van Gogh, choose your poison... outdated IGP or CPU

  36. Question Speculation: RDNA2 + CDNA Architectures thread

    Or i missed something, or It's used already

  37. Question Speculation: RDNA2 + CDNA Architectures thread

    Ah yes, Ampere 7nm confirmed! videocardz...

  38. Question Speculation: RDNA2 + CDNA Architectures thread

    The video and research says 0,09mm2 of silicon per CU... it also regress the performance in some cases...

  39. Question Speculation: RDNA2 + CDNA Architectures thread

    Yeah... i miss read from reddit, sorry

  40. Question Speculation: RDNA2 + CDNA Architectures thread

    The "Infinity cache" trademark links to the patent "adaptive cache"... The patent is exacly the same as found later the .pdf, a crossbar comunication
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