Cinebench isn't best case. I can tell because they literally say they got 15% in specint2006 rate, so cinebench cannot be a best case.
Cinebench is a fairly reliable, well scaling with cores, and quick to do benchmark. Perfect for showing off multicore devices on a stage.
They model things depending on simulations of workloads. If their suite of workloads that they predict will be commonplace performs better with the 5% faster single thread than two extra cores, then they'll make that choice. The 28 core number on Skylake-X was very carefully chosen.
I never said the rest of the system isn't pushed too. There's a balance to strike that AMD and Intel work very hard on figuring out, modeling workloads years in advance, and bet billions on it being the right one. There isn't a correct one answer, but there is a close enough answer for the...
You need single threaded performance to keep increasing together with multi core, there's always going to be inherently serial work that needs to be done, I don't even know why this is debated. No sane microprocessor engineer will tell you that you don't need to keep pushing single threaded...
Amdahls law is far too misused in these discussions. Yes more cores all else being equal does pleatu. But that's never the case. You always increase resources in conjunction with those cores.
It's important to note that using SMT to fill the core in absence of a powerful enough OoO engine to fill the execution pipeline with a single thread is not necessarily a bad thing. It's a conscious trade off, and a very fine balancing point for Intel for years now, as well as AMD with Zen...
It's not really a story of AMD vs Intel in the nanometer war, though obviously it's the most direct comparison we see. Who really outdid Intel was TSMC, through a combination of reasonable and flexible goals on the side of TSMC, and outlandish ones from Intel, on top of not having any back up...
There is nothing tying Polaris or Vega to any specific memory controller. AMD designs GPU's in modular blocks, and the memory controller is just another block that can be mixed and matched. For example Fiji was basically just Tonga scaled up with HBM. Same architecture.
As for Vega 11, it...
They know within a certain range with high certainty what they'll hit. The final frequencies are only nailed down quite late in development.
As for the rest, they're simply keeping more for later. This isn't a launch, you aren't going to get all the information in one go.
Depends on Threadripper volumes.
If for example they sell a lot of TRs, the cost savings by having more dies per wafer could tip over the balance Vs taking defective dies. That's why Intel tends to make a lot of small consumer dies (8c/6c/4c/2c are all different), because at their volumes it...
Had an amusing thought. If the I/O die really has a bunch of L4 cache, and they scale it between EPYC/Threadripper/AM4, that would mean Threadripper should have more L4 than AM4.
That would allow some games on Threadripper to outperform their AM4 counterparts core for core, clock for clock...
Bandwidth needs is just as much down to architecture as core counts. Saying dual channel not being able to feed 16 cores because the previous gen fed 8 cores isn't really an argument. Rome is 16c per dual channel lol
That said, I don't expect price per core to drop significantly with Ryzen...
Time to market and flexibility. Being able to mix and match IP quickly to meet customer demands. It would be great for AMD's semi custom division if any of the Big 7 decided they want a custom I/O chip for their EPYC for whatever reason.
Not certainly. If the controller chip is built to be modular they could make a smaller one specifically for AM4 quite easily. That saves them from another 7nm tape out as the controller is 16nm/14nm.
So server and client would share cores, but the controller/IO die would be specifically per...
vOv
I didn't make any claims about directions Apple will take. I just said there was extreme surprise when Intel revealed their Tiger Lake plans to the executives.
I also completely disagree with your "unimpressive" claims for Ice Lake. Literally a leaked result of a test platform. We don't...
IPC is directly impacted by latency. You can have 20% higher IPC from 20% lower latency if your program is 100% memory latency bound.
Games are on average around 35% bound on my Intel 8600K platform at tuned subtimings and 3400. Dropped to 2400 and default timings and the average is around 40%...
IPC doesn't have much weight in gaming. Zen's biggest deficiency in gaming is the high memory latency. Just look at how gaming gained disproportionally to most software with Zen+.
Larger caches, better pre-fetching, and getting memory latency as low as possible, are the defining factors.
You...
Only effect it would have is power consumption. That's significantly more I/O to power than mobile devices usually have. I wouldn't be surprised if the overall power consumption exceeded the A12's consumption in iPhone.
I know for a fact that happened. I have disgruntled friends who weren't happy with their work going nowhere, now working for Apple. Some of them were there since Yonah.
Food for thought: The fabric and uncore alone on Skylake cores eat about as much power as the TDP of an entire A12 SoC. They have different goals in terms of flexibility and scalability in both the architectural sense and user sense.
Combine that with the different nodes, and how Skylake is a...
Nonsense.
What you see is the result of Intel's 10nm screwing the entire pipeline of new CPU's. There's a lot of 10nm IP waiting to be released that just doesn't find its way anywhere because they can't manufacture it. Skylake isn't the pinnacle of x86, not by a long shot. Even AMD with a...
That's assuming AMD does the strategy of reusing server dies for consumer again. I am not convinced of this, for several reasons.
However I'm not going to elaborate further since the information is behind a paywall.
Personally I expect server dies to diverge from consumer dies in Zen 2.
Are there any plans to bring Optane DIMMS to consumer? Being able to install your OS on near DRAM latency storage would be an incredible way to differentiate from competitors.
NVIDIA won't enter the CPU market mainly because they don't have the know how and R&D budget to start doing anything remotely competitive with Intel or AMD.
You might say NVIDIA has a larger budget than AMD, but remember that AMD already has design methodology and expertise for a high...
I doubt the Arabic money stopped flowing entirely. Rather it shrunk and diverted to more profitable possibilities (FDX). They would be dumb to not develop future nodes, their current nodes won't give them return on investment for all the fabs they bought up.
You might say it's sunk cost, but...
PC enthusiasts live in a semiconductor bubble. The vast majority of volume isn't made on N nodes. Not even on N-1, or N-2 nodes. Heck we're running out of capacity for 200mm wafers, when was that bleeding edge again?
GloFo will be fine, their FDSOI nodes combined with IBM tech is the best in...
Garry Patton of Global Foundries
7LP wasn't cancelled because 12FDX is better. It was cancelled because GlobalFoundries is quitting the leading edge race and going for more financially viable routes.
And no, 22FDX isn't anywhere near 7LP either.
And those performance figures are only valid for small devices. Garry Patton himself said that FinFETs do better than FDSOI on devices like what AMD creates.
RISC-V will be used for microcontollers where ARM currently dominates. Having no licensing fees makes it extremely attractive.
High performance/general purpose stuff is usually highly dependent on a software ecosystem like x86 or ARM have, so displacing them would be, uh, hard.
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